Anas Showk

Performance analysis of LTE protocol processing on an ARM based mobile platform

In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly increased computational demands in LTE and future mobile devices. A virtual prototyping approach is adopted in order to simulate a state-of-the-art mobile phone platform which is based on an ARM1176 core. Moreover a physical layer and base station emulator is implemented that allows for protocol investigations on transport block level at different transmission conditions. By simulating LTE data rates of 100 Mbit/s and beyond, we measure the execution times in a protocol stack model which is compliant to 3GPP Rel.8 specifications and comprises the most processing intensive downlink (DL) part of the LTE L2 data plane. We show that the computing power of a single embedded processor at reasonable clock frequencies is not enough to cope with the L2 requirements of next generation mobile devices. Thereby, Robust Header Compression (ROHC) processing is identified as the major time critical software algorithm, demanding half of the entire L2 DL execution time. Finally, we illustrate that a conventional hardware acceleration approach for the encryption algorithms fails to offer the performance required by LTE and future mobile phones.

Modeling LTE protocol for mobile terminals using a formal description technique

The Long Term Evolution (LTE) radio communication is the upgrade of the current 3G mobile technology with a more complex protocol in order to enable very high data rates. The usage of Model Driven Development (MDD) has arisen as a promising way of dealing with the increasing complexity of next generation mobile protocols. In this paper, a light version of the LTE protocol for the access stratum user plane is modeled using the SDL Suite™ tool. The tool shows easy understanding of the model as well as easy testing of its functionality using simulation in cooperation with Message Sequence Chart (MSC). The simulation result shows that the implemented Specification and Description Language (SDL) guarantees a good consistency with the target scenarios. The system implementation is mapped to multiple threads and integrated with an operating system to enable execution in multi core hardware platforms.

Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform

This article provides a detailed profiling of the layer 2 L2 protocol processing for 3G successor Long Term Evolution LTE. For this purpose, the most processing intensive part of the LTE L2 data plane is executed on top of a virtual ARM based mobile phone platform. The authors measure the execution times as well as the maximum data rates at different system setups. The profiling is done for uplink UL and downlink DL directions separately as well as in a joint UL and DL scenario. As a result, the authors identify time critical algorithms in the protocol stack and check to what extent state-of-the-art hardware platforms with a single-core processor and traditional hardware acceleration concepts are still applicable for protocol processing in LTE and beyond LTE mobile devices.

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

In this paper we present an efficient software implementation of the Advanced Encryption Standard (AES) used in the confidentiality algorithm of the Long Term Evolution (LTE) protocol. Our implementation is based on slicing and merging the bytes of several data blocks to exploit processors architecture width for multi-block encryption. In addition, an appropriate lookup table and data organization in memory are applied, combined with media processing instructions in order to enhance the performance of AES in embedded environments. Other optimized software implementations from literature are also explored and evaluated in comparison to the proposed implementation with respect to processing throughput and energy consumption using a multi-core based mobile phone platform. Simulation results show that the proposed implementation is the fastest among other implementations and achieves improvements in performance up to 69% while providing 59% of energy savings. Moreover, the presented implementation is scalable for multi-core execution. When running on two cores, it fulfills the LTE data rate of 100 Mbit/s and extends energy savings to 68%, leading to a total of 13 times improvement in energy efficiency.

Optimal resource management for a model driven LTE protocol stack on a multicore platform

The Long Term Evolution (LTE) is the successor technology of the 3G wireless system. The high data rates enabled by LTE can benefit from a strong computational power provided by todays high-performance embedded processors. In this work we therefore utilize a multicore processor to increase the LTE system throughput in the mobile terminal. We investigate the dynamic memory allocation scheme for the LTE protocol stack, modeled using Specification and Description Language (SDL), as the underlying issue with migrating from single to multiple cores. We discover that, under some schemes, multicore performance becomes inferior to a single-core, especially in case of intensive dynamic memory allocation and deallocation. By modifying the SDL systems run time kernel we implement a static memory management scheme. This is supplemented by a selective usage of resource protection in single- and dual-core situations. As a result, an increase of the system throughput by about 75% can be observed when migrating from one core to two cores.

An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals

In this paper we present an efficient hardware architecture for accelerating the Robust Header Compression version 2 (ROHCv2) algorithm in Long Term Evolution (LTE) mobile devices. The proposed hardware accelerator and its software variant are evaluated on an FPGA-based SoC. Our results show that the advised hardware architecture provides processing speeds (2.9 Gbit/s) beyond LTE-Advanced. Moreover, it increases the compression speed by 14-fold and reduces power consumption by 37%, compared to the software solution. The hardware is further optimized to handle multiple packet flows by employing a shared context buffer, thereby lowering the energy consumption of the ROHC hardware by 21% and ceasing degradation in compression rate.

An Energy Efficient Multi-Core Modem Architecture for LTE Mobile Terminals

Since data rate in wireless communication systems has exponentially increased during the last decade, serious efforts are considered to fulfill their target requirements. Therefore, providing a satisfactory hardware to support high data rates while minimizing power consumption is a key design challenge for Long Term Evolution (LTE) mobile terminals. In this paper we introduce an optimized parallel software architecture for LTE mobile terminals using an energy aware scheduling and load balancing. We show that the proposed software architecture on single, dual, triple and quad-core hardware platforms leads to up to 39% energy savings. In addition, different hardware design options are investigated in order to minimize the average power consumption. The homogeneous multi-core with four cores processing the optimized LTE software saves about one quarter of the energy compared to a single-core running at higher clock frequency achieving the same data rate. Considering statistics for the mobile user behavior, the homogeneous multi-core with four cores proves to provide the minimum average power consumption compared to the other hardware architectures considered in this work.

A Parallel Software Architecture for the LTE Protocol on a Multi-Core Mobile Modem

Coming wireless communication standards like Long Term Evolution (LTE) promise to bring a drastic increase in data rate for the end user. To facilitate this evolution, sophisticated technology for the mobile equipment is required. Most research focuses on the signal processing in the physical layer whereas the computational capabilities for protocol processing are neglected. This paper describes novel software architecture and load balancing for the LTE protocol stack that allows concurrent execution on a multi-core processor and thus allows for exploiting all the advantages like higher performance through parallelism at low power consumption. The layered protocol is developed using Specification and Description Language (SDL). In addition, the LTE protocol stack is parallelized and executed on a multi-core processor, by employing the SDL processes concurrency. Moreover, the LTE system is scheduled on multi-core by customizing the SDL scheduler to implement a data pipeline scheduler. Furthermore, a new load balancer scheme is proposed by moving the load balancer to the modem subsystem’s layer and using the SDL process migration concept. The performance of the LTE protocol implementation using the new scheme beats the classic thread migration scheme by more than 50% on single as well as multi-core platforms. The data throughput using the new scheme increases on two, three, or four cores, compared to single core, by about 195%, 290%, and 360%, respectively, and thus shows an excellent scalability for up to three cores and still giving reasonably good results for four cores. A Parallel Software Architecture for the LTE Protocol on a Multi-Core Mobile Modem

SDL/virtual prototype co-design for rapid architectural exploration of a mobile phone platform

In this paper we present a new hardware/software co-design methodology for embedded systems, where software components written in Specification and Description Language (SDL) execute on a soft-model of a hardware platform, a so called Virtual Prototype (VP). The proposed approach enables fast exploration of difierent hardware and software design options at high level of abstraction in order to make early system design decisions. We prove our approach by considering the Long Term Evolution (LTE) communication stack as a use case for the architectural exploration of our mobile terminal. The open source L4/Fiasco microkernel is deployed as a Real-Time OS to run the modem application represented by the LTE SDL-modelled protocol stack. We profile and analyze the system performance by measuring average and maximum packet processing times under various hardware and software conditions. Thereby, we are able to rapidly obtain an eficient design point that provides 80% packet processing speedup against other unoptimized implementations while meeting the required timing constraints and maintaining a good balance between area and power consumption.