Felix Bruns

An Evaluation of Microkernel-Based Virtualization for Embedded Real-Time Systems

Devices for the mobile market have to satisfy a set of challenging constraints. In addition to the classical power, reliability and cost constraints, modern devices often have to be open to third party applications and at the same time provide a closed and secure environment for system functionality. In current systems, this antagonism is solved by maintaining a physical separation of subsystems with contrary constraints. Virtualization technology is a promising solution to safely merge conflicting subsystems on a single processor which leads to huge cost benefits and higher flexibility. Microkernel based hyper visors are an attractive choice for virtualization, due to their reliability and robustness. However, the involvement of real-time constraints remains a challenging factor. In this paper, we investigate how the security and isolation features of the L4/Fiasco microkernel impact real-time applications by comparing thread switching times and interrupt latencies to those of a conventional Real-time Operating System (RTOS). In addition, we demonstrate that microkernel based systems require significantly more cache resources than traditional systems. Finally, we investigate the performance loss caused by cache and TLB interference imposed by an application subsystem which runs in parallel to the real-time subsystem.

Acceleration of the L4/Fiasco microkernel using scratchpad memory

In this paper we analyze the potential of using scratchpad memory in embedded devices to accelerate the operation of the L4/Fiasco microkernel affecting basically all applications on top of the kernel including virtualization software. We examine several low-level L4 system calls using a virtual prototype of Infineons S-GOLD® platform for mobile phones based on an ARM11 processor. We present a profiling strategy identifying critical parts of the microkernel to be placed on the scratchpad memory. Applying this approach we achieve a worstcase speedup of up to 29% with one page of scratchpad memory (4 kB) and up to 63% with two pages. With regard to the real-time capability of Fiasco, worst-case interrupt latency can be improved by almost 45% with only 4 kB of scratchpad memory.

On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices

In this paper we present a new on-the-fly hardware acceleration approach, based on a smart Direct Memory Access (sDMA) controller, for the layer 2 (L2) downlink protocol stack processing in Long Term Evolution (LTE) and beyond mobile devices. We use virtual prototyping in order to simulate an ARM1176 processor based hardware platform together with the executed software comprising an LTE protocol stack model. The sDMA controller with diff erent hardware accelerator units for the time critical algorithms in the protocol stack is implemented and integrated in the hardware platform. We prove our new hardware/software partitioning concept for the LTE L2 by measuring the average execution time per transport block in the protocol stack at di fferent activated on-the-fly hardware acceleration stages in the sDMA controller. At LTE data rates of 100 Mbit/s, we achieve a speedup of 24% compared to a pure software implementation by enabling the sDMA hardware support for header processing in the protocol stack. Furthermore, an activation of the complete on-the-fly hardware acceleration in the sDMA controller, including on-the-fly deciphering, leads to a speedup of more than 50 %. Finally, at transmission conditions with more computational demands and data rates up to 320 Mbit/s, we obtain acceleration ratios of almost 80 %. Investigations show that our new sDMA on-the-fly hardware acceleration approach in combination with a single-core processor off ers the required computational power for next generation mobile devices.

An optimized parallel and energy-efficient implementation of SNOW 3G for LTE mobile devices

Multi-core processors are becoming attractive for mobile devices because of the performance speedups and power savings they might attain. In this paper we employ such processors to investigate the SNOW 3G ciphering algorithm in the Long Term Evolution (LTE) protocol stack. In particular, we introduce several software optimizations, and present a novel parallel implementation of the algorithm. The proposed parallel design and its serial counterparts are then benchmarked using a simulated mobile phone platform. Evaluation results show that optimizations applied to the serial implementation saves 57% of energy consumption and shortens the execution time to the half. Moreover, the proposed parallel implementation meets the LTE speed, while reducing the energy consumption by 70%, and improving the energy efficiency by a factor of eight.

Low-power smart industrial control

Measurement equipment for process control in the chemical industry has to face severe restrictions due to safety concerns and regulations. In this work, we discuss the challenges raised by safety concerns and explain how they lead to strong power and energy constraints in the design of industrial measurement equipment. We argue that a comprehensive strategy in the design and implementation of hardware and software on one hand, and power management on the other hand is required to satisfy these constraints. Furthermore we demonstrate solutions for the power efficient design of the computing system and bus topology in an industrial environment.

Optimal resource management for a model driven LTE protocol stack on a multicore platform

The Long Term Evolution (LTE) is the successor technology of the 3G wireless system. The high data rates enabled by LTE can benefit from a strong computational power provided by todays high-performance embedded processors. In this work we therefore utilize a multicore processor to increase the LTE system throughput in the mobile terminal. We investigate the dynamic memory allocation scheme for the LTE protocol stack, modeled using Specification and Description Language (SDL), as the underlying issue with migrating from single to multiple cores. We discover that, under some schemes, multicore performance becomes inferior to a single-core, especially in case of intensive dynamic memory allocation and deallocation. By modifying the SDL systems run time kernel we implement a static memory management scheme. This is supplemented by a selective usage of resource protection in single- and dual-core situations. As a result, an increase of the system throughput by about 75% can be observed when migrating from one core to two cores.

Virtualization for safety-critical, deeply-embedded devices

Even today, safety-critical systems in many fields of application use separate processors to isolate software of different criticality from another. The resulting system architecture is non-optimal in regard to flexibility, device size and power consumption. These drawbacks can be prevented by the use of partitioning operating systems that enable the integration of applications with different criticality on a single processor. However, their application for deeply-embedded devices, that are characterized by strict resource constraints and the lack of advanced processor features such as memory-management units (MMU), is challenging. In this work, we show that the impact of virtualization on performance and predictability is smaller in the field of deeply-embedded devices than in more complex systems, making it a compelling choice as a partitioning technology. We present a hypervisor that provides time and space partitioning for an MMU-less system, as well as mechanisms for communication and resource sharing. To satisfy the strict power and resource constraints found in deeply-embedded devices, we focus on solutions with a minimal runtime overhead. Furthermore, the hypervisor is integrated with the processor power management, often enabling significant power savings in the resulting system architecture.

Exploration of energy efficient acceleration concepts for the ROHCv2 in LTE handsets

In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.

Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals

In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPPs Long Term Evolution (LTE). This concept already demonstrated a significant performance benefit over conventional approaches by on-the-fly header decoding and deciphering for the data plane of the LTE protocol stack layer 2 in downlink direction. With a low-level hardware implementation we prove that also from an architectural point of view the sDMA controller is suitable for LTE terminals. Compared to conventional hardware acceleration, chip area and energy consumption are reduced by 10% and 56%, respectively. Furthermore, we show that the header decoding has the highest architectural impact on the sDMA controller. By a change of the hardware/software partitioning within the header decoding unit, the chip area of the sDMA controller is decreased by 35%, while it consumes 39% less power. The improvement compared to the conventional approach (with the same modification) is then even increased to 17% (area) and 59% (energy).

A hierarchical domain model for safety-critical cyber-physical systems in process automation

Cyber-physical systems (CPS) integrate computation with physical processes. For the last years, CPS have been in the focus of research and are getting adopted in multiple domains like health care, automotive and smart factories. The use of CPS promises dynamic adaption of systems to changing environmental and economic conditions through autonomous CPS decisions based on the physical process. In industrial process automation, research and adoption of CPS have to account for the severe safety restrictions that dominate the system design in this domain. To transfer the benefits of CPS application to process automation, the CPS must be able to formally verify the safety of its autonomous reconfiguration decisions. This paper proposes a domain model for safety-critical CPS in industrial process automation to serve as foundation for formal CPS algorithms.