André Scavennec

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ges50-GHz- clock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD- HBT equations. These large signal models have allowed the design of 50-GHz clocked 50 G Decision and 100 G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

InP DHBT technology and design methodology for high-bit-rate optical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions.

Semiconductor technologies for higher frequencies

An overview of the semiconductor active devices available for 100-GHz and 100-Gb/s applications is given, based on semiconductor properties and device requirements. The most widespread technologies are then described, and then the status of competing technologies is given in two different areas: frequency dividers, which illustrate the suitability of a technology for high-speed digital circuits, and oscillators, which illustrate their behavior in analog circuits applications. The aim of this presentation was to illustrate the variety and potential impact of these evolving technologies with consistently increasing frequency performance. While the improvement of device performance relied for a long time only on the reduction of dimensions permitted by progress in lithography, heterostructures and strain engineering are now powerful means by which to enhance performance, in both speed and power, to a level that opens a door to the 100-GHz and 100-Gb/s application arena.

Lateral design of InP/InGaAs DHBTs for 40 GBIT/s ICs

InP-based HBTs are now available exhibiting cut-off frequency well over 100 GHz even at 1 mA. In this paper, a 40 Gbit/s IC-oriented InP/InGaAs DHBT technology is presented with maximum Ft of 170 GHz and Fmax over 210 GHz with BV/sub ce0/>9 V, specific features of this technology have been developed to increase the design flexibility: high current gain and frequency performances are kept over a large range of collector currents (from 1 mA to 100 mA) and for various dimensions, this is achieved through size-specific lateral transistor design optimization, these features are required for high-performance 40 Gbit/s ICs designed for optical transmission systems, in which careful transistor optimization has to be performed according to its function in the circuit.

Study of Failure Mechanisms in InP/GaAsSb/InP DHBT Under Bias and Thermal Stress

This paper presents results of aging tests performed on InP/GaAsSb/InP HBTs leading to the identification of a typical failure mechanism. Submitted to combined thermal and current stresses, HBTs under test present a current gain degradation. The modeling of the current gain degradation with stress time allows to evaluate a time to failure and reveal its thermal dependence through the extraction of an activation energy of 0.94plusmn0.03 eV. Discussion on the physical origin of the failure mechanism concludes on (i) the possible localization of the failure mechanism near the surface of the device at the semi-conductor-passivation interface and (ii) the possible presence of pre-existing defects triggered to become electrically active by the stress conditions.

InP/GaAsSb/InP multifinger DHBTs for power applications

We report the performances of multifinger GaAsSb/InP double heterojunction bipolar transistors (DHBTs) designed for high power applications. 2-finger 15times1 mum² devices demonstrate maximum f_T of 221 GHz and maximum f_max of 293 GHz when biased at J_C = 370 kA/cm² and V_CE = 1.4V. Moreover we investigate the limitation of frequency performances with the number of fingers.

Evidence of RTS noise in emitter-base periphery of InP/GaAsSb/InP HBT

This paper presents low frequency noise (LF) measurements on InP/GaAsSb/InP HBTs. The spectral analysis of the dominant base noise source SIb has allowed to identify the 1/f noise and a RTS noise component. From LF noise measurements as a function of the temperature, the parameters of the traps responsible for the RTS noise signature have been extracted. An activation energy close to 200 eV with a capture cross-section near 1times10-18 cm2 have been determined.

107 Gbit/s demultiplexing photoreceivers comprising pin- and pinTWA frontends

Demultiplexing photoreceivers, composed of either pin or pinTWA packaged frontends and subsequent packaged InP-HBT-based demultiplexers are reported for 107 Gbit/s operation, paving the way to ultra compact co-packaged pin/pinTWA-DEMUX receivers.

Comparative collector design in InGaAs and GaAsSb based InP DHBTs

In this paper we compare the base-collector transit time of GaAsSb- and InGaAs-based double heterojunction bipolar transistors (DHBT) at low and high collector current. Using a ldquotype IIrdquo base-collector heterostructure leads to a simpler design to increase the operating current range of the devices.

InP DHBT Technology Development for High Bitrate Mixed-Signal IC Fabrication

The development and optimization of an InP DHBT process suiting high bitrate mixed-signal IC fabrication is described. Full-rate 40 Gb/s ICs are reported to validate this technology relevance. Undergoing technology improvements are described, which will allow higher performance and/or lower power consumption.