Muriel Riet

Generation and Transmission of 21.4-Gbaud PDM 64-QAM Using a Novel High-Power DAC Driving a Single I/Q Modulator

We generate a single-carrier 21.4-Gbaud polarization-division-multiplexed (PDM) 64-ary quadrature-amplitude-modulated (QAM) signal (256.8-Gb/s line rate) using a single in-phase/quadrature (I/Q) optical modulator driven by 8-level electrical waveforms from a novel high-power digital-to-analog converter (DAC). We measure a required optical signal-to-noise ratio of 29.5 dB (0.1-nm reference bandwidth; 10-3 bit-error rate), 4.6-dB off the theoretical limit. Using ultra-large-area fiber, we achieve 400-km single-channel transmission. The DAC was also used to obtain excellent results with quadrature-phase-shift-keyed and 16-QAM signals at 21.4 Gbaud.

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ges50-GHz- clock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD- HBT equations. These large signal models have allowed the design of 50-GHz clocked 50 G Decision and 100 G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

MSI InP/InGaAs DHBT technology: beyond 40 Gbit/s circuits

We present current results obtained on IC-oriented OPTO+ InP DHBT lab technology. Transistors with 180/210 GHz F/sub t//F/sub max/, current gain of 50 and BV/sub ce0/=7V are currently fabricated with >99% fabrication yield. Uniformity measurements show a standard deviation on F/sub t/ and F/sub max/ lower than 2% and lower than 5% on all investigated parameters. In a second part DHBT-specific modelling issues are discussed. A 68 Gbit/s selector has been obtained and a 40 Gbit/s master-slave D-type flip-flop (MS-DFF) has been reproducibly fabricated with >50% functional yield using this technology.

InP DHBT technology and design methodology for high-bit-rate optical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions.

DC-100-GHz frequency doublers in InP DHBT technology

Broad-band monolithic integrated active frequency doublers operating in dc-100-GHz frequency range are presented. Circuits are fabricated in a self-aligned InP double heterojunction bipolar transistor process. Three integrated doubler versions have been designed. Inductive peaking and active splitting effects are quantified and compared. Circuit measurements give sinusoidal output waveform at 100 GHz with an rms timing jitter of 400 fs. Circuits have a maximum conversion gain of +1 dB at 60 GHz. the fundamental suppression is better than 24 dB in the whole frequency range.

InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations.

A High Conversion-Gain

The paper presents analysis and design of a Q-band subharmonic mixer (SHM) with high conversion gain. The SHM consists of a local oscillator (LO) frequency doubler, RF pre-amplifier, and single-ended mixer. The SHM has been fabricated in a high-speed InP double heterojunction bipolar transistor (DHBT) technology using coplanar waveguide structures. To the best of our knowledge, this is the first demonstration of an SHM using InP DHBT technology at millimeter-wave frequencies. The measured results demonstrate a conversion gain of 10.3 dB at 45 GHz with an LO power of only 1 mW. The fundamental mixing product is suppressed by more than 24 dB and the output is around . The mixer is broadband with a conversion gain above 7 dB from 40 to 50 GHz. The conversion gain for the fabricated SHM is believed to be among the best ever reported for millimeter-wave SHMs.

Q

We report a 2:1 selector-driver based on a differential distributed amplifier realized in a 0.7-μ m indium phosphide double heterojunction bipolar transistor technology. From transistors reaching fT/fmax of 320/380 GHz and a breakdown voltage (BVCEO) of 4.5 V, the selector-driver provides a differential eye amplitude of up to 6.2 and 5.9 VPP at up to 100 and 112 Gb/s, respectively, for a power consumption of 3.8 W, achieving a record swing-speed product of 620 and 660 VGb/s, respectively.

-Band InP DHBT Subharmonic Mixer Using LO Frequency Doubler

The design of high-speed circuits and optimization of function of technological and geometrical parameters are presented. Various modeling aspects are discussed, such as model accuracy for InP heterojunction bipolar transistor and modeling with technological and geometrical parameters. MUX-driver design and optimization for 40-Gb/s ETDM transmission is presented. The impact of collector thickness (W/sub c/) on driver performances is evaluated and assessed by circuit fabrication and measurements. Results of 40-Gb/s electrical measurements and optical experiment with realized MUX-driver module are presented.

A Large-Swing 112-Gb/s Selector-Driver Based on a Differential Distributed Amplifier in InP DHBT Technology

More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.