P. Berdaguer

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ges50-GHz- clock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD- HBT equations. These large signal models have allowed the design of 50-GHz clocked 50 G Decision and 100 G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

A Large-Swing 112-Gb/s Selector-Driver Based on a Differential Distributed Amplifier in InP DHBT Technology

We report a 2:1 selector-driver based on a differential distributed amplifier realized in a 0.7-μ m indium phosphide double heterojunction bipolar transistor technology. From transistors reaching fT/fmax of 320/380 GHz and a breakdown voltage (BVCEO) of 4.5 V, the selector-driver provides a differential eye amplitude of up to 6.2 and 5.9 VPP at up to 100 and 112 Gb/s, respectively, for a power consumption of 3.8 W, achieving a record swing-speed product of 620 and 660 VGb/s, respectively.

Lateral design of InP/InGaAs DHBTs for 40 GBIT/s ICs

InP-based HBTs are now available exhibiting cut-off frequency well over 100 GHz even at 1 mA. In this paper, a 40 Gbit/s IC-oriented InP/InGaAs DHBT technology is presented with maximum Ft of 170 GHz and Fmax over 210 GHz with BV/sub ce0/>9 V, specific features of this technology have been developed to increase the design flexibility: high current gain and frequency performances are kept over a large range of collector currents (from 1 mA to 100 mA) and for various dimensions, this is achieved through size-specific lateral transistor design optimization, these features are required for high-performance 40 Gbit/s ICs designed for optical transmission systems, in which careful transistor optimization has to be performed according to its function in the circuit.

InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits

In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.

InP DHBT Mux-Drivers for Very High Symbol Rate Optical Communications

This paper reports on very high speed large swing drivers suitable for the generation of high symbol rate spectrally efficient optical transmission signals. To accommodate available data rate, these circuits integrate multiplexing stages. Fabricated using our InP DHBT technology (FT and FMAX >300 GHz, BVCE0 ~5 V), these circuits include NRZ and Multi-Level drivers; they have been used to generate OOK, QPSK and QAM signals in optical transmission experiments at bitrates beyond 100 Gbps.

InP/GaAsSb/InP multifinger DHBTs for power applications

We report the performances of multifinger GaAsSb/InP double heterojunction bipolar transistors (DHBTs) designed for high power applications. 2-finger 15times1 mum² devices demonstrate maximum f_T of 221 GHz and maximum f_max of 293 GHz when biased at J_C = 370 kA/cm² and V_CE = 1.4V. Moreover we investigate the limitation of frequency performances with the number of fingers.

InP DHBT mixed-signal specific ICs for advanced 40 Gb/s transmitters

Various mixed signal ASICs have been designed to address 40 Gb/s optical transmission experiment needs, and realized specific research transmitters. These circuits have been fabricated using a self-aligned InP DHBT process. Three transmitters have been assembled using these IC: i) an EAM-based; ii) a DDA-based; iii) a PSBT/DPSK transmitter. Design and characterization of these circuits are reported.

InP HBT self-aligned technology for 40 Gbit/s ICs: fabrication and CAD geometric model

InP/InGaAs DHBT technology for 40 Gb/s ICs is first presented. For these circuit applications, a sufficient breakdown voltage (>5 V), a static gain around 50, cutoff frequencies (f/sub T/) and maximum oscillation frequencies (f/sub max/) greater than 100 GHz are needed. High performance InP/InGaAs DHBT grown by chemical beam epitaxy (CBE) are reported with 125 GHz f/sub T/, 128 GHz f/sub max/ and a gain of 50 at a current density of 1/spl times/10/sup 5/ A/cm/sup 2/. Devices geometry optimisation is performed using a geometric model based on a set of analytical equations. This tool allows not only technological optimisation but also function-adapted individual sizing of the devices in the circuits.

Up-to-50-GHz-clock InP DHBT digital ICs and optical system experiments

In this paper, we describe various custom digital ICs fabricated using our InP DHBT technology, operating at a clock rate up to 50 GHz. We also present the results of some 40+ Gbit/s system experiments these circuits have enabled.

Comparative collector design in InGaAs and GaAsSb based InP DHBTs

In this paper we compare the base-collector transit time of GaAsSb- and InGaAs-based double heterojunction bipolar transistors (DHBT) at low and high collector current. Using a ldquotype IIrdquo base-collector heterostructure leads to a simpler design to increase the operating current range of the devices.