Andrea Fantini

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Random telegraph noise (RTN) is an important intrinsic phenomenon of any logic or memory device that is indicative of the reliability and stochastic variability in its performance. In the context of the resistive random access memory (RRAM), RTN becomes a key criterion that determines the read disturb immunity and memory window between the low (LRS) and high resistance states (HRS). With the drive towards ultra-low power memory (low reset current) and aggressive scaling to 10 × 10 nm2 area, contribution of RTN is significantly enhanced by every trap (vacancy) in the dielectric. The underlying mechanisms governing RTN in RRAM are yet to be fully understood. In this study, we aim to decode the role of conductance fluctuations caused by oxygen vacancy transport and inelastic electron trapping and detrapping processes. The influence of resistance state (LRS, shallow and deep HRS), reset depth and reset stop voltage (VRESET-STOP) on the conductance variability is also investigated.

Stochastic variability of vacancy filament configuration in ultra-thin dielectric RRAM and its impact on OFF-state reliability

Considering SET and RESET to be dynamic stochastic processes involving the generation-recombination and drift-diffusion of multiple oxygen ions / vacancies, we examine the microscopic statistical changes in the shape of the filament during multiple switching cycles in ultra-thin low-power HfOx-based RRAM. The effect of forming compliance, dielectric microstructure, multi-layer dielectric films and Al-doping on the variability in the filament geometry is investigated based on the quantum point contact (QPC) formulation [1, 2]. The stability (reliability) of the filament in the OFF-state to non-equilibrium vacancy-induced perturbations is evaluated using the disturb voltage (VDIST). Microscopic changes of the defect arrangement in the OFF-state have a big influence on the filament stability. The final configuration of the filament in the OFF-state is bimodal with a finite non-zero probability of being in the QPC mode or entering the tunnel barrier (TUN) mode.

Modeling the Impact of Reset Depth on Vacancy-Induced Filament Perturbations in

Random telegraph noise in resistive switching memory devices is governed by two distinct mechanisms—oxygen vacancy perturbations in the filament as well as the electron trapping–detrapping phenomenon. In this letter, we focus on the dominant role of vacancies in governing the stability of the filament in the high resistance state and characterize the dependence of the read disturb voltage

{\rm HfO}_{2}

(V_{rm DIST})

RRAM

on the depth of the reset level during switching. Our slow voltage ramp read disturb tests at different reset levels indicate the possibility of filamentary instability even for read voltages lower than the standard value of 0.10 V. These experimental trends can be well explained using the quantum point contact model for conduction in the filament, as deeper reset levels induce very steep potential gradients at the two ends of the constriction that make the filaments highly unstable and susceptible to structural modifications due to vacancy generation and/or transport during memory read operation.

Sub-10 nm low current resistive switching behavior in hafnium oxide stack

In this letter, a tip-induced cell relying on the conductive atomic force microscope is proposed. It is verified as a referable replica of an integrated resistive random access memory (RRAM) device. On the basis of this cell, the functionality of sub-10u2009nm resistive switching is confirmed in hafnium oxide stack. Moreover, the low current switching behavior in the sub-10u2009nm dimension is found to be more pronounced than that of a 50u2009×u200950u2009nm2 device. It shows better ON/OFF ratio and low leakage current. The enhanced memory performance is ascribed to a change in the shape of the conductive filament as the device dimensions are reduced to sub-10u2009nm. Therefore, device downscaling provides a promising approach for the resistance optimization that benefits the RRAM array design.

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

A Cautionary Note When Looking for a Truly Reconfigurable Resistive RAM PUF

The reconfigurable physically unclonable function (PUF) is an advanced security hardware primitive, suitable for applications requiring key renewal or similar refresh functions. The Oxygen vacancies-based resistive RAM (RRAM), has been claimed to be a physically reconfigurable PUF due to its intrinsic switching variability. This paper first analyzes and compares various previously published RRAM-based PUFs with a physics-based RRAM model. We next discuss their possible reconfigurability assuming an ideal configuration-to-configuration behavior. The RRAM-to-RRAM variability, which mainly originates from a variable number of unremovable vacancies inside the RRAM filament, however, has been observed to have significant impact on the reconfigurability. We show by quantitative analysis on the clear uniqueness degradation from the ideal situation in all the discussed implementations. Thus we conclude that true reconfigurability with RRAM PUFs might be unachievable due to this physical phenomena.

Design-technology co-optimization for OxRRAM-based synaptic processing unit

In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification accuracy (94%) including device variability. To our knowledge, this is the first paper to discuss the tradeoff between single and multi-device synaptic weight in terms of design and technology using silicon data. We have demonstrated that high level of variability can be handled by the neuromorphic algorithm. The results presented in the paper has been obtained from 1Mb array.

Algorithms to Survive: Programming Operation in Non-Volatile Memories

Non-Volatile memories offer the possibility to maintain the stored digital information over years without a power supply. This requires programming mechanisms that physically modify the memory cell: this physical alteration must be “hard” in order to guarantee the non-volatility of the stored information. We could say that, in general, the harder it is to intentionally modify the cell, the better is the data retention over time.