Augusto Redolfi

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Abstract When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Improvement of data retention in HfO 2 /Hf 1T1R RRAM cell under low operating current

One of the key concerns related to low operating current (<;50μA) of RRAM is the degraded data retention. Most of the retention studies so far focused on high switching current range. In this work, we investigate the retention degradation mechanism at low programming current range (10-40μA) and identify the key parameters that control retention in oxygen vacancy filamentary switching HfO<;sub>2<;/sub>/Hf 1T1R RRAM cells. Based on this understanding we demonstrated significant improvement in retention by adding an additional thermal budget into our process flow. The impact of the Forming process on retention property was also investigated and Forming/SET conditions were optimized to improve the retention without increasing the operation current.

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM): An area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window resistive switching cell

We report a novel self-compliant and self-rectifying resistive switching memory cell, with area-scalable switching currents, featuring a set current density of ~5nA/nm2 (<;9uA for a 40nm-size cell), high on-state half-bias nonlinearity of 102 and low reset current density of <;0.6nA/nm2 (<;1uA@40nm size). The cell can be operated at below ±4V/10ns, with a large on/off window of >102 and retention extrapolates to 10yr at 101°C. The switching stack is fully based on ALD processes, using common high-k dielectrics and has a thickness of <;10nm, meeting the 3D Vertical RRAM requirements. Moreover, we point out the nonlinearity-low-current operation interdependence and discuss the scaling potential of the areal switching RRAM for reliable sub-μA current operation in the 10nm-cell size realm.

Ultrathin Metal/Amorphous-Silicon/Metal Diode for Bipolar RRAM Selector Applications

We propose a novel metal/silicon/metal (MSM) selector using ultrathin undoped amorphous silicon (a-Si) for resistive-RAM selector application. The new selector behaves as a bidirectional diode, showing a high current drive (~2.2 MA/cm)2, high selectivity (~240 for 1/2 bias), fast switching speed , and excellent endurance ( at target drive current). The doping-free a-Si structure alleviates the dopant-induced variability concerns for ultrascaled devices and eliminates the need for a dopant-activation anneal. Circuit simulations show feasibility of 1-Mb array, with over 25% read margin and 70% write margin, when using the new MSM structure as a selector for a HfO2-based resistive switching memory element.

High-Performance Metal-Insulator-Metal Tunnel Diode Selectors

We report on a novel high-performance metal-insulator-metal tunnel diode, with ultrathin atomic layer deposited Ta2O5, for bidirectional selector applications in resistive switching memory. The diode exhibits high drive current of over 105 A/cm2, high nonlinearity, and fast turn-on and turn-off times in the below-ns range. A very good uniformity for structures down to 40 nm size and excellent ac endurance is demonstrated, well exceeding the stand-alone nonvolatile memory requirements.

High-drive current (>1MA/cm 2 ) and highly nonlinear (>10 3 ) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance

An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is to further increase the A.R. of the TSV interconnection. This requires the integration of highly conformal thin films deposition techniques in TSV flows, particularly for metallization. In this study, seed layer enhancement is applied to regular PVD Cu seed for metalizing TSV of diameter of 2μm and aspect-ratio 15:1. The results reported in this paper open a new path for process integration of high A.R. TSVs and provide a versatile and reliable building block for achieving the high density interconnects required for tomorrows 3D electronics devices.