Andrea Vigna

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-mum CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm 2 and 0.7 mm2 die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth

A CMOS 5 nV

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 mum CMOS occupying 1.65 mm2 is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an active-Gm-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 divide 68 dB, while the input-referred noise (IRN) is 5 nV/radicHz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.

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This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN standard requirements. It can be digitally programmed to process WLAN 802.11a/b/g and UMTS signals, by adjusting the DAC conversion frequency and the low-pass filter cutoff frequency. For the WLAN mode, the DAC operating frequency and the filter bandwidth are set to 100 and 11 MHz, respectively, while for the UMTS mode, they are equal to 50 and 2.11 MHz. The device is realized in a 1.2-V 0.13-mum standard CMOS technology. The die area occupation, equal to 0.9mm2, has been minimized by optimizing the component sharing for the two operation modes. The proposed circuit achieves a 30.4 dBm third-order output referred intermodulation intercept point (OIP3) for the WLAN mode, and a 31.5 dBm-OIP3 when configured for the UMTS mode, while the spurious-free dynamic range is 58 dB for WLAN mode, and 60 dB for UMTS mode. The power consumption is optimized according to the operation mode and is 19.44 mW in WLAN mode and 16.8 mW in UMTS mode

Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

A DAC+filter is realized in a 0.13/spl mu/m CMOS technology to operate in a multistandard (WLAN/UMTS) transmitter. The 0.8mm device allows programming the 8 bit DAC sampling frequency (100MHz/50MHz) and the 4th-order low-pass filter bandwidth (11 MHz/2.11MHz) to satisfy the 8 bit WLAN/9bit UMTS standards, consuming 11mW/8.4mW from a single 1.2V supply. For both standards the OIP3 is larger than 29dBm and the SFDR is 54dB for WLAN, 61dB for UMTS.

A 1.2- V 30.4-dBm OIP3 Reconfigurable Analog Baseband Channel for UMTS/WLAN Transmitters

A low-power reconfigurable analog baseband block for UMTS/WLAN transmitters is presented. The law-power pe6ormance is guaranteed by the innovative architecture that allows to directly connect the output DAC current with the reconstruction analog filter. The DAC and the baseband filter, have been designed in a 0.13pm CMOS technology with a power supply limited to I.2K The current consumption, has been optimized for the selected UMTS or WLAN standard and it equal to 7.9mA and 10mA, respectively.

A low-power, low-voltage (11mW/8.4mW, 1.2V) DAC+filter for multistandard (WLAN/UMTS) transmitters

This paper presents the trade-offs in dimensioning a 10 bit, 80 MHz current steering DAC for wireless-LAN transmitters. All the performance parameters are considered, trying to optimize static performance, dynamic performance and area occupation. Behavioral and transistor level simulations are then used to validate the proposed mathematical analysis.

Low-power reconfigurable baseband block for UMTS/WLAN transmitters

For the present and up-coming WLAN applications (802,11a/g, 802.11n, 802.16), a transmission baseband architecture uses a 600-MS/s current-steering DAC with a passive output load to perform the baseband signal processing, avoiding the use of any active reconstruction filter. In a 0.13-mum CMOS technology the DAC consumes 2.4 mW from a single 1.2-V supply voltage. The DAC exhibits a full-scale SFDR of 68 dB for an input signal frequency of 12 MHz and a full-scale dynamic range of 9.7 bits between 0 and 10 MHz. These data correspond to the best reported figure of merit, if compared with state-of-the-art digital-to-analog converters

Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter

We present the design trade-offs for dimensioning the baseband blocks (DAC and reconstruction filter) of a direct conversion transmitter for the UMTS standard. A Matlab model performs a time domain analysis to evaluate the impact of each baseband block non-ideality on the overall transmitter performance. The proposed approach has been used to design a 0.13 /spl mu/m CMOS test-chip implementing the DAC and filter blocks.

A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN 802.11 and 802.16 Wireless Transmitters

This paper presents a reconfigurable analog baseband channel for multistandard receivers. The circuit, consisting of two variable gain amplifiers and a low-pass filter, fulfills the requirements of GSM, WCDMA (UMTS), WLAN (IEEE 802.11a/b/g), and Bluetooth. The gain, bandwidth and power consumption of the circuit are changed through a digital control word depending on the selected standard. Simulation results, including all of the tests prescribed by the different standards, confirm the validity of the proposed solution. The in-band IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm for UMTS/WLAN respectively, while the power consumption is 51.7mW/55mW in the two cases

Behavioral analysis and dimensioning of UMTS transmitters baseband blocks

The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.