Nicola Ghittori

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-mum CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm 2 and 0.7 mm2 die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth

Low-power 6-bit flash ADC for high-speed data converters architectures

The design of low-power, medium resolution flash converter is presented. The goal is to provide a basic cell with state-of-the art figure of merit thus permitting low-power data converter architectures with a more flexible use of flash ADC cells. The designed 6-bit flash uses interpolation and V/I converters that operate as preamplifier stage of latches. Circuit simulations show a figure of merit as low as 1.2 pj/conv-lev at 100-MS/s sampling frequency and 3.3-V analog supply voltage

A 1.2- V 30.4-dBm OIP3 Reconfigurable Analog Baseband Channel for UMTS/WLAN Transmitters

This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN standard requirements. It can be digitally programmed to process WLAN 802.11a/b/g and UMTS signals, by adjusting the DAC conversion frequency and the low-pass filter cutoff frequency. For the WLAN mode, the DAC operating frequency and the filter bandwidth are set to 100 and 11 MHz, respectively, while for the UMTS mode, they are equal to 50 and 2.11 MHz. The device is realized in a 1.2-V 0.13-mum standard CMOS technology. The die area occupation, equal to 0.9mm2, has been minimized by optimizing the component sharing for the two operation modes. The proposed circuit achieves a 30.4 dBm third-order output referred intermodulation intercept point (OIP3) for the WLAN mode, and a 31.5 dBm-OIP3 when configured for the UMTS mode, while the spurious-free dynamic range is 58 dB for WLAN mode, and 60 dB for UMTS mode. The power consumption is optimized according to the operation mode and is 19.44 mW in WLAN mode and 16.8 mW in UMTS mode

A low-power, low-voltage (11mW/8.4mW, 1.2V) DAC+filter for multistandard (WLAN/UMTS) transmitters

A DAC+filter is realized in a 0.13/spl mu/m CMOS technology to operate in a multistandard (WLAN/UMTS) transmitter. The 0.8mm device allows programming the 8 bit DAC sampling frequency (100MHz/50MHz) and the 4th-order low-pass filter bandwidth (11 MHz/2.11MHz) to satisfy the 8 bit WLAN/9bit UMTS standards, consuming 11mW/8.4mW from a single 1.2V supply. For both standards the OIP3 is larger than 29dBm and the SFDR is 54dB for WLAN, 61dB for UMTS.

Low-power reconfigurable baseband block for UMTS/WLAN transmitters

A low-power reconfigurable analog baseband block for UMTS/WLAN transmitters is presented. The law-power pe6ormance is guaranteed by the innovative architecture that allows to directly connect the output DAC current with the reconstruction analog filter. The DAC and the baseband filter, have been designed in a 0.13pm CMOS technology with a power supply limited to I.2K The current consumption, has been optimized for the selected UMTS or WLAN standard and it equal to 7.9mA and 10mA, respectively.

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-

A 0.076 mm2 12b 28 nm 600 MS/s 4-way time interleaved ADC with on chip buffer is presented. The usage of a subranging scheme consisting of a coarse SAR ADC followed by an incremental ΔΣ fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The ADC area has been optimized by using a segmented charge-sharing charge-redistribution DAC. The prototype achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming 26 mW.

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This paper presents the trade-offs in dimensioning a 10 bit, 80 MHz current steering DAC for wireless-LAN transmitters. All the performance parameters are considered, trying to optimize static performance, dynamic performance and area occupation. Behavioral and transistor level simulations are then used to validate the proposed mathematical analysis.

ADC With On-Chip Buffer in 28 nm CMOS

For the present and up-coming WLAN applications (802,11a/g, 802.11n, 802.16), a transmission baseband architecture uses a 600-MS/s current-steering DAC with a passive output load to perform the baseband signal processing, avoiding the use of any active reconstruction filter. In a 0.13-mum CMOS technology the DAC consumes 2.4 mW from a single 1.2-V supply voltage. The DAC exhibits a full-scale SFDR of 68 dB for an input signal frequency of 12 MHz and a full-scale dynamic range of 9.7 bits between 0 and 10 MHz. These data correspond to the best reported figure of merit, if compared with state-of-the-art digital-to-analog converters

Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter

We present the design trade-offs for dimensioning the baseband blocks (DAC and reconstruction filter) of a direct conversion transmitter for the UMTS standard. A Matlab model performs a time domain analysis to evaluate the impact of each baseband block non-ideality on the overall transmitter performance. The proposed approach has been used to design a 0.13 /spl mu/m CMOS test-chip implementing the DAC and filter blocks.

A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN 802.11 and 802.16 Wireless Transmitters

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to the current pulses drawn from voltage supplies in mixed analog-digital CMOS ICs. To this end, two test chips were designed in 0.18-μm CMOS technology. The two test chips were integrated and then mounted on a board with and without package to compare measurements on chips mounted in package and mounted on board. To ensure that the differences between measurements are only due to the assembling technique, the same printed circuit boards were used for both chip-in-package and chip-on-board. Moreover, the experimental setup was carefully arranged so as not to introduce further disturbances due to external connections or noise sources. Both ICs were extensively simulated by using a realistic model of on-chip and off-chip parasitics to study what happens in the analog section when digital switching noise is injected. Simulations results, confirmed by test chip measurements, demonstrate that disturbances due to switching currents in digital blocks propagate through substrate, package, and interconnection parasitics and affect analog voltages, thus degrading the circuit performance. Therefore, reduction of parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends.