Andreas Leininger

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques

This paper introduces the concept of utilizing the timing flexibility of automatic test equipment (ATE) when designing X-tolerant test compactors. Redundant information is generated by the compactor and transferred to the ATE at a frequency k times higher than the scan shift frequency. This technique is different than current X-tolerant compactors where the necessary redundant information is generated on additional compactor outputs. If the Compactor design can take into account the ATE capabilities, the knowledge of the redundancy can be efficiently used. The ATE will select the relevant information out of the compacted test response, which then leads to a reduction of the ATE compare data by a factor k. In the best case this method can be applied without extra costs related to the higher frequency. The benefit of this approach is a higher parallel test factor due to the reduced number of output pins. This paper explains the capabilities of the employed ATE which need to be taken into account when designing an X-tolerant compactor using a higher output data rate. The method is also demonstrated on a shift register which works at a multiple of the scan shift frequency.

Masking of X-Values by Use of a Hierarchically Configurable Register

In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.

Masking of X-values by Use of a Hierarchically Configurable Register

In this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are undefined states (X-values). In the presence of X-values during test a considerable number of the scan cells cannot be observed at the compressed outputs. We present a new hierarchical two-step method of X-masking to achieve a high observability of scan cells and to reduce the overhead for X-masking. For every scan-shift cycle the generated X-mask is either set to be active or not. By this method the number of X-values at the compacted outputs is considerably reduced. The remaining small number of X-values can be tolerated by an X-tolerant compactor. To implement this method a hierarchically configurable register is used.

X-tolerant Test Data Compaction with Accelerated Shift Registers

Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.

Accelerated Shift Registers for X-tolerant Test Data Compaction

In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.

A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*

We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second test sequence is derived from the first in a straightforward manner and the same test pattern source is used for both test sequences. If an interval contains only a single failing vector, the algebraic analysis is guaranteed to identify it. We also show analytically that if an interval contains two failing vectors, the probability that this case is interpreted as one failing vector is very low. We present experimental results for the ISCAS benchmark circuits to demonstrate the use of the proposed method for identifying failing test vectors.