Thomas Rabenalt

On-chip evaluation, compensation and storage of scan diagnosis data

Technology and product ramp-up suffers increasingly from systematic production defects. Diagnosis of scan-test fail data plays an important role in yield enhancement, as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production may lead to significant test time overhead. A new on-chip architecture is presented that evaluates scan-test results and stores relevant scan diagnostic information on chip. Scan diagnostic data is unloaded for offline analysis after the scan test has been finished. Unloading scan diagnostic data from chip requires only very little test time overhead. Moreover, the proposed technique is automatic test equipment independent and accelerates test program development. A detailed implementation example, based on a state-of-the-art SoC device, is given.

Masking of X-Values by Use of a Hierarchically Configurable Register

In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.

Masking of X-values by Use of a Hierarchically Configurable Register

In this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are undefined states (X-values). In the presence of X-values during test a considerable number of the scan cells cannot be observed at the compressed outputs. We present a new hierarchical two-step method of X-masking to achieve a high observability of scan cells and to reduce the overhead for X-masking. For every scan-shift cycle the generated X-mask is either set to be active or not. By this method the number of X-values at the compacted outputs is considerably reduced. The remaining small number of X-values can be tolerated by an X-tolerant compactor. To implement this method a hierarchically configurable register is used.

High Performance Compaction for Test Responses with Many Unknowns

We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficiently load x-masking data into a masking logic. A method eliminating the need for explicit mask control signals using ATE timing flexibility is also introduced. The proposed compactor can efficiently be employed in multi-chip testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment

This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The techniques applied are on-loadboard compare and shared driver. Already known on a concept level for an on-chip approach, in this paper the transfer to an on-loadboard solution is presented. Emphasis is put on production related aspects. Practical experience, challenges, and pitfalls are described to allow a better assessment of risks and benefits of the investigated methods.

Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique

This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.