Andreas Neyer

A fully integrated all-digital PLL based FM-radio Transmitter in 90 nm CMOS

A fully integrated FM-radio Transmitter (TX) is fabricated in 90 nm CMOS. It is based on an all-digital phase-locked-loop (ADPLL) and designed for co-integration in future nanoscale CMOS mobile applications. The in-band synthesizer phase noise is measured below −85 dBc/Hz for the loop bandwidth of 110 kHz. The 0.25 mm2 chip consumes 12.4 mW using a 1 V supply and provides 87 MHz to 108 MHz output frequency.

A FM-radio transmitter concept based on an all-digital PLL

A stereo FM-radio transmitter with Radio Data System (RDS) support based on an all-digital PLL is presented. It has been designed as a fully integrated single-chip transmitter in a 90-nm CMOS technology to be compatible with digital deepsubmicrometer processes. Target application of the proposed system is the cointegration with baseband processors and transmitters for mobile communication systems. Nowadays mobile phones have a lot of multimedia capabilities e. g. an integrated MP3 player. The proposed transmitter enables a mobile device to stream audio data to a FM receiver which is popular and existing in most households world wide. RDS support allows to send additional information e. g. title and artist of a song. As mobile applications are the main target for the transmitter great attention has been attached to saving power and area. Therefore, the presented transmitter works on a 1V supply voltage and is aimed for using a 32.768 kHz reference crystal oscillator instead of the commonly used 26MHz reference oscillator while still providing wideband frequency modulation capability.

Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS

The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90nm CMOS process. For this application the oscillator frequency of 3.05–3.45GHz is divided by 32 or 36 to cover the frequency span of 87.5–108.0MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7mW at 1V supply voltage. This setup shows a phase noise below −154 dBc Hz at 20MHz offset. The chip area utilised by one DCO is 260 × 500 µm. Simulations show the performance of this DCO is state-of-the-art.

An all-digital PLL for satellite based navigation in 90 nm CMOS

New wireless communication devices comprehend more and more functionality. The number of existing and supported communication and RF standards is increasing. On the other hand the integration of analog and mixed-signal RF circuitry becomes more complex, as advanced deep-submicrometer CMOS processes usually do not offer any analog extension. On the system level the use of reconfigurable multimode architectures becomes more and more important. On the circuit level more digital intensive approaches become possible and are implemented instead of classical pure analog or mixed-signal topologies. In this work an all-digital PLL for a multimode shared RF low-power receiver for satellite based navigation is presented. It has been designed as a fully integrated single-chip PLL in a 90 nm CMOS technology to be compatible with digital deep-submicrometer processes. Target application of the proposed system is the co-integration with other RF circuitry and digital baseband processors for mobile communication systems. As mobile applications are the main target for the PLL great attention has been attached to saving power and area. Therefore, the presented PLL works on a 1 V supply voltage.

Calibration Technique for σΔ Modulation Loops using Radio-Frequency Phase Detection

A novel calibration scheme for predistortion ΣΔPLLs is proposed in this paper. In contrast to present calibration algorithms this technique offers a digital representation of the high frequency phase characteristic. The architecture uses minimum chip area by synchronously sampling the data content of an asynchronous divider chain. Using this technique to detect the phase difference during a step response allows to determine the real loop gain within 7 mus with an accuracy better than 0.1%. Obtaining this, the deviation from the desired loop gain can be adjusted by a digitally controlled charge pump in order to derive the wanted loop transfer function. This is mandatory for predistortion modulation loops. The architecture is designed by systemtheoretical calculation of the loop behaviour and verified by mixed signal VHDL-AMS simulations.

Novel Optimization Criteria for Loop Filter Design of Type II PLLs

The dynamics of phase locked loops (PLLs) are heavily influenced by the right choice of the loop filter parameters. A new approach for determining these parameters to meet the specification of telecommunications standards optimally is presented in this paper. The most common optimization criterium is to minimize the integral error over time of the step response. In a telecommunications system, it is more important to keep the instantaneous frequency error within a specified tolerance bandwidth around a desired frequency. When the power amplifier is integrated with the transceiver circuitry, specifications are even harder to meet. For this reason, an optimization method has been developed that features short settling times with inherent stability for any chosen loop bandwidth