Jan Henning Mueller

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

This paper presents an RFDAC based transmitter for wireless mobile and connectivity applications in a 65 nm CMOS technology. The transmitter RFDAC has a segmented architecture employing 4 LSB and 16 MSB unit cells for each I and Q path, thus providing a resolution of 8 bit + signum. Switchable LO drivers and unit cells with current shutdown are used to reduce power dissipation when transmitting signals with high PAPR such as IEEE 802.11 (WLAN) or 3GPP Long Term Evolution (LTE). The frontend is capable of transmitting an 64 QAM-OFDM WLAN signal at a center frequency of 1 GHz with an output power of -8 dBm and an EVM of 4.66 %. Analog power dissipation is 34 mW, clock and LO divider use less than 10 mW, and the digital block consumes about 87 mW. The area of the frontend is about 0.4 mm2.

Maximum power point tracker for small number of solar cells connected in series

Maximum power point tracking (MPPT) techniques are widely applied in photovoltaic (PV) systems to fully utilize the PV array output power. Major challenges for MPPT are rapidly changing irradiance conditions and partial shading of the PV cells. These issues become even more severe for mobile applications, such as solar cells on the roof of electric vehicles. This paper deals with the implementation of a fast, fully integrated MPPT for a small number of solar cells connected in series with respect to mobile applications. For this special requirements, different open and closed loop MPPTs have been compared and evaluated. The optimal MPPT has hence been implemented. Furthermore, a bypass concept based on MOSFETs instead of bypass diodes is applied to utilize the maximum available power of the solar cells. The MPPT has been built in VHDL and realized in a 150nm CMOS technology. Due to its adaptive step size and its high sampling rate, the MPPT reaches the MPP within less than 0.65 ms with consumes less than 6.2 μW.

Photovoltaic output power improvement applying DC-DC converters on submodule level

This paper investigates the output energy of power optimizers for partial shading conditions and introduces a novel concept for boosting output energy in such situations. A MATLAB/Simulink model on cell level is developed for comparing the output energy of the different circuits to the theoretical maximum. It is shown that for power optimizers even small amounts of shading reduce the output energy significantly. Based on these results, the so called submodule concept is introduced, which overcomes these drawbacks. By integrating ASICs into the PV modules, the number of series connected solar cells is decreased, while additional costs are kept low and high reliability is maintained. The submodule concept provides the largest output energy improvement for low amounts of shading. From an economic point of view this is the most important operating area, since the theoretical harvestable energy decreases with increasing shading. Therefore, the submodule concept is a good and economic solution for increasing the overall energy yield of PV installations.

12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology

Todays general lighting development is driven by improvements in semiconductor-based systems. It is expected that solid-state lighting (SSL) will dominate general lighting in the near future. Two main challenges that must be met in SSL are the reduction of the bill of materials (BOM), and an increase in functionality. In [1], a floating DC-DC buck controller is presented. This controller adds to the BOM, as every device of the power path is discrete and the ASIC can only drive a single LED string. In contrast to that, [2] offers a high-current fully integrated power stage. However, several external passives are introduced and the technology inhibits stacking multiple LEDs for high luminous efficacy. To overcome this, [3] presents an integrated HV power path with only the inductor as an external component. Ina parallel development, [4] reports an LED driver similar to [3], but that uses a discrete Schottky diode for asynchronous rectification. In fact, [1-4] demonstrate single output LED drivers without additional functionality or full color spectrum. To overcome these drawbacks in light spectrum and control, [5] presents a 3-channel LED driver. However, the external passives are numerous, which significantly impairs the overall BOM.

A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump

This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.

A Multi-Frequency Multi-Standard Wideband Fractional-

This paper presents a wideband fractional- N frequency synthesizer design with a low-effort adaptive calibration technique for ΣΔ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital-analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

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This paper presents a novel multi-standard digital low-IF receiver, which provides low-power low-complexity, flexible and robust performance for short distance communication applications. Over the various incoming data rates and carrier frequencies, the corresponding symbol timing is recovered by the ΣΔ modulated frequency divider from fractional-N synthesizer, and the carrier frequency offset is calibrated by direct digital synthesizer generated intermediate frequency. The proposed digital receiver is fully integrated with 130 nm CMOS technology, occupying 0.83 mm2 area with 4.5 mW. Through the verification in an FPGA, the measurement results show a great potential in flexible and cost oriented applications.

PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

A fully integrated FM-radio Transmitter (TX) is fabricated in 90 nm CMOS. It is based on an all-digital phase-locked-loop (ADPLL) and designed for co-integration in future nanoscale CMOS mobile applications. The in-band synthesizer phase noise is measured below −85 dBc/Hz for the loop bandwidth of 110 kHz. The 0.25 mm2 chip consumes 12.4 mW using a 1 V supply and provides 87 MHz to 108 MHz output frequency.

A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration

Photovoltaic applications require very small current and voltage ripples at the output of the solar cells to avoid power losses due to deviations from the maximum power point. Digital control offers optimization potentials to reduce this ripple without increasing the requirements on the analog-to-digital converters or the loop delay. This paper investigates the achievable current ripple reduction for two different digital current prediction algorithms applied to a hysteretic controlled photovoltaic submodule converter. A basic method relying on the continuity of the inductor current and an advanced algorithm, which compensates loop delay have been implemented in VHDL. Both methods are compared in structure and simulation results. The basic current prediction reduces the current ripple by 11 %, whereas the advanced current prediction decreases the ripple in total by 26 %. The whole controller including the advanced current prediction requires less than 0.1mm2 in a 150nm CMOS technology.

A fully integrated all-digital PLL based FM-radio Transmitter in 90 nm CMOS

A low complexity low power transmitter architecture for narrow band applications is presented, consisting of two single polar transmitters for the 900MHz and the 2.4GHz band, respectively. Only a single 1.8GHz local oscillator signal is used employing self-upmixing for the 2.4 GHz output. The transmitter supports arbitrary IQ modulation schemes and OFDM to fulfill the Bluetooth 4.0 “Smart”, IEEE 802.15.4/Zigbee, IEEE 802.15.4g “SUN” (Smart Metering Utility Networks), and IEEE 802.11ah Sub-GHz WLAN standards. Special emphasis is placed on keeping the digital signal processing power efficient while preserving enough flexibility to fulfill all mentioned standards. The low complexity polar transmitter frontends are also described in detail. The intended output power is 24dBm for the lower band and 13dBm for the upper band to achieve high ranges even without additional external power amplifiers. The transmitter is used in a system-on-a-chip RF transceiver for smart utility networks and the internet of things. It has been fabricated in a 130-nm CMOS technology.