Björn Thorsten Thiel

System architecture of an RF-DAC based multistandard transmitter

In this paper the system concept of a radiofrequency digital-to-analog converter (RF-DAC) based multistandard transmitter is presented. The RF-DAC combines DA converter and up-conversion mixer in a single building block. Thereby, the analog baseband blocks are eliminated and replaced by easily reconfigurable digital blocks. Requirements on the digital and mixed-signal blocks are discussed. Spurious emissions are a major issue of this ‘direct digital modulator’. This is especially true for multiradio devices with several receivers running simultaneously and in close proximity to the transmitter. Therefore, a maximum emission limit is formulated and especially critical frequency bands are identified. Several techniques for reducing the spurious emissions are discussed and performance requirements for an LTE transmitter and its main building block are found. System simulations demonstrate the feasibility of the concept.

Lowpass delta-sigma modulator with digital upconversion for switching-mode power amplifiers

This work presents a lowpass ΔΣ based transmitter frontend suitable for software defined radios (SDRs). ΔΣ modulation is utilised to generate an RF signal suitable for driving highly efficient switching-mode power amplifiers. The whole transmitter frontend is implemented in the digital domain up to the upconversion. Thus, high reconfigurability and flexibility necessary for SDR is achieved. This work presents two implementations methods for lowpass ΔΣ modulator based transmitter frontends for SDR applications. The circuit design in a 90nm CMOS process and a discrete implementation utilising a field programmable gate array (FPGA) are discussed. Feasibility of the concept is demonstrated by simulation for the integrated implementation and by measurements for the FPGA solution.

System architecture of an all-digital GHz transmitter using pulse-width/position-modulation for switching-mode PAs

This paper presents a novel concept for direct-pulse-width/position-modulation (PWPM) in an all-digital transmitter by using a parallel baseband PWPM and high speed digital up-conversion. By parallel calculation and subsequent serialization of the digital PWPM signal carrier frequencies above 1 GHz become feasible. PWPM enables the usage of highly efficient switching-mode power amplifiers (SMPA) and direct control of the output power. Because PWPM modulator can be completely implemented in the digital, time discrete domain, all analogue baseband blocks can be dropped and replaced by reconfigurable digital blocks. The only remaining mixed-signal and analogue blocks are the multiplexer and the power amplifier. Requirements on the digital and mixed-signal blocks are discussed. Feasibility of the concept is demonstrated by system and circuit simulations showing the possibility of using digital PWPM in wireless applications.

A FM-radio transmitter concept based on an all-digital PLL

A stereo FM-radio transmitter with Radio Data System (RDS) support based on an all-digital PLL is presented. It has been designed as a fully integrated single-chip transmitter in a 90-nm CMOS technology to be compatible with digital deepsubmicrometer processes. Target application of the proposed system is the cointegration with baseband processors and transmitters for mobile communication systems. Nowadays mobile phones have a lot of multimedia capabilities e. g. an integrated MP3 player. The proposed transmitter enables a mobile device to stream audio data to a FM receiver which is popular and existing in most households world wide. RDS support allows to send additional information e. g. title and artist of a song. As mobile applications are the main target for the transmitter great attention has been attached to saving power and area. Therefore, the presented transmitter works on a 1V supply voltage and is aimed for using a 32.768 kHz reference crystal oscillator instead of the commonly used 26MHz reference oscillator while still providing wideband frequency modulation capability.

Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS

The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90nm CMOS process. For this application the oscillator frequency of 3.05–3.45GHz is divided by 32 or 36 to cover the frequency span of 87.5–108.0MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7mW at 1V supply voltage. This setup shows a phase noise below −154 dBc Hz at 20MHz offset. The chip area utilised by one DCO is 260 × 500 µm. Simulations show the performance of this DCO is state-of-the-art.

Optimized mismatch shaping for an RF-DAC based OFDM transmitter

This work presents an element selection logic (ESL) for a radio frequency digital to analog converter (RF-DAC) based multistandard transmitter in 65 nm CMOS. After introducing the transmitter system and the basics of mismatch shaping, the ESL is applied to an OFDM transmitter. The design is optimized with respect to the signal properties and synthesis is done for the mentioned CMOS technology. Simulation results show a significant improvement of the signal quality in the desired band.

Digitally controlled pulse-width-pulse-position modulator in an 1.2V 65 nm CMOS technology

This paper presents a pulse-width and position modulator (PWPM) topology suitable for digital centric polar transmitter frontends suitable for software defined radios. PWPM enables the usage of highly efficient switching-mode power amplifiers (SMPA) and direct control of the output power. The presented first implementation of the modulator targets 3GPP and Long Term Evolution (LTE) base-stations and mobile devices operating in the bands E-UTRA frequency bands V, V I and XX. The proposed modulator generates all possible phases by a delay lock loop. A combination of two multiplexer circuits and an AND-gate allows to digitally select the wanted phase and duty cycle. The achievable phase and time resolution is 11:2° and 35 ps at 900MHz, which is sufficient for these applications. The feasibility of the implementation was verified by simulations on extracted layouts.

Reconstruction lumped-element bandpass filter suitable for lowpass delta-sigma RF transmitters

This paper proposes a filter realised using only lumped-element components, implemented as a highly selective bandpass filter suitable for lowpass delta-sigma (LPΔΣ) RF transmitters. The proposed filter is characterised by low insertion loss, high selectivity and a transfer function tailored for filtering the close-up out-of-band noise of LPΔΣ RF transmitters. The circuit design is based on a modified loaded-stub ring-resonator structure, however, implemented using 4 π-shape lumped-element resonators with LC tanks. The measurements show good agreement with simulation and the proposed filter provides a fractional 3-dB bandwidth of 14.3 %, insertion loss of less than 1.6 dB, suppression of more than 18 dB on both sides of the desired band, and a sharp cut-off frequency response. This filter is combined with the delta-sigma transmitter to show the effective reduction of the out-of-band quantisation noise signals.