Andreas Rupp

How to build a Generic Model of complete ICs for system ESD and electrical stress simulation

For precise system ESD simulation the transient chip behavior needs to be modeled accurately. As there are several typical characteristics possible (e.g. diode breakdown, snapback-element or forward diode) a straight forward methodology to build a generic model for transient behavior with destruction limits in SPICE is presented. This enables full-system transient ESD and electrical stress simulation for system robustness evaluation.

Active clamp design for on-chip GUN protection

On-chip active clamps show attractive performance for the component-level ESD protection like HBM, but suffer usually from their weakness for short-pulse and high-current events like the first peak of IEC 61000-4-2 (GUN) pulses. This disadvantage can be overcome by adequate active clamp design, resulting in an area efficient active clamp GUN protection.