Andreas Schallenberg

OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

OSSS+R: Modelling and Simulating Self-Reconfigurable Systems

High level description languages and tools lack appropriate support to specify reconfigurable systems. We propose a methodology for partially self-reconfigurable systems, which consists of a SystemC based language, simulation abilities and the perspective of automated synthesis. We introduce a configuration management infrastructure, which frees designers of error-prone and time consuming tasks

Designing for Dynamic Partially Reconfigurable FPGAS with Systemc and OSSS

This paper presents a new approach to design embedded systems based on dynamic partial reconfigurable FPGAs. The approach is intended to allow designing of systems with runtime reconfiguration without explicit specification by the designer. The design entry point is the HDL OSSS, a SystemC extension allowing for synthesizable object orientation and polymorphism.

The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems

Todays heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task clue to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.

PolyDyn—Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this chapter, we present a SystemC™-based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow.

SPP1148 booth: Seamless design flow for reconfigurable systems

Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases floorplanning, bus macro instantiation, and bitstream generation. We show OSSS+R modelling, simulation and Part-E in a hands-on fashion. Synthesis to VHDL is demonstrated, too.

Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)

Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes. However, the use of reconfigurable devices within large systems greatly increases the design complexity. The designer´s task gets even harder when the goal is a resource efficient solution. Constructing a good design requires the consideration of many design alternatives. With today´s complex systems and the resulting degrees of freedom the designer should be assisted by sophisticated design space exploration tools. However, all known system-level design space exploration tools do not exploit the potentials dynamic hardware reconfiguration exposes. Moreover, the implementation of selected solutions poses an additional challenge and also requires a cycle-level simulation. This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level design space exploration. Dynamisch rekonfigurierbare Chips erlauben es, bei großen Systemen Ressourcen einzusparen. Sie dienen als dynamisch programmierbare Einheiten für laufzeitkritische Anwendungen. Leider erhöht der Einsatz dieser Chips die Entwurfskomplexität drastisch. Die Aufgabe wird noch schwieriger, wenn eine ressourceneffiziente Lösung gefordert ist. Um dabei eine gute Lösung zu finden, müssen viele Entwurfsalternativen untersucht werden, wobei bei der heutigen Komplexität der Systeme und der Anzahl an Freiheitsgraden der Entwickler durch Werkzeuge unterstützt werden sollte. Leider gibt es bis heute keine Explorationswerkzeuge auf Systemebene, die auch das Potential der Laufzeitrekonfigurierung ausnutzen. Der vorliegende Beitrag stellt eine neue Entwurfsmethode vor, um die genannten Aufgaben zu lösen. Dazu werden aktuelle Explorations-, Partitionierungs- und Simulationsverfahren herangezogen. Das mittels mehrerer Iterationsverfahren gewonnene Explorationsergebnis unterstützt dann den Entwickler bei der letztendlichen Implementierung.

A high level constant coefficient multiplier power model for power estimation on high levels of abstraction

Early power estimation in current designflows becomes more important nowadays. To meet this need, power estimation even on the algorithmic level has become an important step in the typical design flow. This helps the designer to choose the right algorithm right from the start and much optimisation potential can be used due to the focus on the crucial parts. In particular, algorithms for digital signal processing as applied in mobile communication systems are very power sensitive. Such algorithms massively contain multiplications with constants on parts of digital filters. In this paper we propose on the one hand our new decomposition algorithm for (nearly) optimal synthesis of constant coefficient multipliers which we use for the evaluation of our new power model. On the other hand we propose a new power model based on the canonical signed digit (CSD) approach which can be used very fast and where the deviation of the power compared to the time consuming decomposition is 4.9%.