Philipp A. Hartmann

OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

Non-invasive Power Simulation at System-Level with SystemC

Due to the increasing algorithmic complexity of today’s embedded systems, consideration of extra-functional properties becomes more important. Extra-functional properties like timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at system and higher levels. In this paper we present an approach for non-invasive augmentation of functional SystemCTM TLM-2.0 components with power properties. The I/O behaviour of a TLM-2.0 component will be observed by a Protocol State Machine (PrSM) that generates trigger events to stimulate a Power State Machines (PSM). The PSM describes the component’s internal power states and transitions and transitions between them. Each component’s PSM is connected with a frequency and voltage dependent power model. We present first evaluation results of different IP components and compare our system-level power traces generation with state-of-the-art gate-level power simulations in terms of accuracy and simulation speed.

The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems

Todays heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task clue to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.

Run-time resource management based on design space exploration

A main challenge in todays embedded system design is to find the perfect balance between performance and power consumption. This paper presents a run-time resource management framework for embedded heterogeneous multi-core platforms. It allows dynamic adaptation to changing application context and transparent optimization of the platform resource usage following a distributed and hierarchical approach. A Global Resource Manager (GRM) is running in parallel with the central manager of the application on the host processor of the platform. Each IP core of the platform can execute its own Local Resource Manager (LRM), and the GRM conforms to practices of each LRM. The operating points managed by the GRM are identified in a design-space exploration phase as a set of Pareto-optimal configurations of the application and their impacts with regards to the quality of experience, performance and energy consumption. The GRM has already been integrated in a POSIX version of an audio-driven video surveillance application in order to maximize its QoE parameters with respect to the battery duration and the energy budget of the platform, used to analyze the GRM efficiency.

An ESL timing & power estimation and simulation framework for heterogeneous socs

Consideration of an embedded systems timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable proto-types are generated from a functional C/C++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios.

Efficient modelling and simulation of embedded software multi-tasking using SystemC and OSSS

Since the software part in todaypsilas designs is increasingly important, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduler, priorities, mapping) has to be explored in early design phases. In this paper, we present an extension of the existing SystemCtrade-based OSSS design flow regarding software multi-tasking in system models. The simulation of the OSSS software run-time model supports different scheduling policies, as well as efficient timing annotations, and deadlines. Inter-task communication is modelled via user-defined shared objects. The impact of timing annotation granularity on the achievable simulation performance is studied. As a result, a lazy synchronisation scheme is proposed, that is based on omitting SystemC time synchronisations, that do not have observable effects on the application model.

PolyDyn—Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this chapter, we present a SystemC™-based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow.

COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.

Modelling control systems in SystemC AMS — Benefits and limitations

In this paper the modelling of a physical control system with SystemC AMS is described. The presented example, a crane controller, is compared with a Matlab/Simulink model in terms of simulation performance and accuracy. Due to numerical stability issues of the canonical implementation of the physical model, an external solver is integrated into the simulation.