Andreia Melo

Development system for FPGA-based digital circuits

The paper discusses some new hardware and software tools that can be used for the design of virtual circuits based on dynamically reconfigurable FPGAs. With the aid of these tools we can implement a system that requires some, hardware resources R/sub c/, on available hardware that has resources R/sub h/, where R/sub c/>R/sub h/. The main idea of the approach supported by these tools is the rational combination of FPGA capabilities with some proposed methods for producing a modifiable specification, together with a novel technique for architectural and logic synthesis, which has been incorporated into the new design environment.

Synthesis tools and design environment for dynamically reconfigurable FPGAs

This paper discusses a range of problems in architectural and logic synthesis of digital devices and suggests practical approaches, methods, and tools for the automatic translation of a behavioural specification into a hardware implementation using a dynamically reconfigurable FPGA of the XC6200 family. The work described in this paper covers two basic areas. Firstly, new FPGA-oriented methods for behavioural synthesis of virtual digital circuits within predefined scopes are presented Secondly, an integrated design environment for logic synthesis (IDELS) is described which has been implemented as an extension of commercially available tools. IDELS permits synthesis in accordance with the developed design flow and offers very powerful run-time debugging facilities, including support for dynamic reconfiguration.

Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs

The paper discusses the models, methods and software tools included in an Integrated Design Environment for Logic Synthesis (IDELS) that has been developed in Visual C++ and can be used for PC computers running under Windows 95/98. It is able to solve a range of problems related to the design of digital systems and their components based on dynamically reconfigurable FPGAs of the XC6200 family. The paper focuses primarily on the integrated features, the basic capabilities and the main packages of the environment itself, rather than the details of how it was implemented. However, the basic ideas behind the methods used, and some of the approaches to implementing the environment are considered, together with some of the problems that we had to address.

Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs

This paper discusses methods and software tools that we have developed for the specification, verification, implementation and debugging of control circuits. The specification method that we have adopted is based on the use of Hierarchical Graph-Schemes. The circuit implementation model is a Hierarchical Finite State Machine, which supports the top-down decomposition of the control algorithms. The application input/output interface provides links with other external tools that perform synthesis and implementation tasks. Some of the utilities we have developed, such as the random control algorithm generator, allow many useful supplementary tasks to be handled and provide powerful assistance for experiments. In particular, the tools have been used to implement Hierarchical Finite State Machines in the Xilinx XC6200 dynamically reconfigurable FPGAs.