Andrew D. Carter

Al2O3 Growth on (100) In0.53Ga0.47As Initiated by Cyclic Trimethylaluminum and Hydrogen Plasma Exposures

The influence of hydrogen plasma treatment before atomic layer deposition of aluminum oxide on In0.53Ga0.47As is investigated. Experiments on untreated, trimethylaluminum-treated, hydrogen-plasma treated, and iterative hydrogen plasma/trimethylaluminum-treated samples are compared in the context of interface trap density, Dit. Through the conductance method, it was found that five cycles of two s, 20 mT, 100 W hydrogen plasma alternating with 40 msS of trimethylaluminum dose prior to dielectric growth resulted in a reduction of interface trap density (0.2 eV below the conduction band edge) from 4.6×1012 eV-1 cm-2 for untreated samples to 1.7×1012 eV-1 cm-2 for treated samples.

Influence of gate metallization processes on the electrical characteristics of high-k/In0.53Ga0.47As interfaces

The influence of different gate metal deposition processes on the electrical characteristics of dielectric/III-V interfaces is investigated. Al2O3 and HfO2 dielectrics are grown on In0.53Ga0.47As channels and top metal electrodes are deposited by either thermal evaporation or electron beam deposition. It is shown that metal-oxide-semiconductor capacitors with electron beam evaporated electrodes exhibit substantially larger midgap interface trap densities than those with thermally evaporated electrodes. The damage caused by electron beam metallization can be mitigated by subsequent, long anneals in forming gas.

III-V MOSFETs: Scaling laws, scaling limits, fabrication processes

III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the inversion layer depth, and increasing the channel 2-DEG density of states. We here describe both nm self-aligned fabrication processes and channel designs to address these scaling limits.

Substitutional-Gate MOSFETs With Composite

We report enhancement-mode composite-channel (In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As) MOSFETs fabricated using a substitutional-gate process, with n⁺ relaxed InAs source-drain regions formed by regrowth by molecular beam epitaxy. A device with 70-nm gate length and 2-nm In_0.53Ga_0.47As/3.5-nm InAs/3-nm In_0.53Ga_0.47As channel showed a peak transconductance of greater than 0.76 mS/μm at <i>V</i>_ds = 0.4 V and showed <i>Id</i> = 0.5 mA/μm at <i>V</i>_ds = 0.4 V and <i>V</i>_gs - <i>V</i>_th = 0.7 V. The subthreshold swing at <i>V</i>_ds = 0.1 V was 130 mV/dec.

( \hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}/\hbox{InAs}/\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As})

We compare the DC characteristics of planar In0.53Ga0.47As channel MOSFETs using AlAs0.56Sb0.44 barriers to similar MOSFETs using In0.52Al0.48As barriers. AlAs0.56Sb0.44, with ∼1.0 eV conduction-band offset to In0.53Ga0.47As, improves electron confinement within the channel. At gate lengths below 100 nm and VDS = 0.5 V, the MOSFETs with AlAs0.56Sb0.44 barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In0.52Al0.48As barrier to thermionic emission from the N + In0.53Ga0.47As source over the In0.53Ga0.47As/In0.52Al0.48As heterointerface. A 56 nm gate length device with the AlAs0.56Sb0.44 barrier exhibits 1.96 mS/μm peak transconductance and SS = 134 mV/dec at VDS = 0.5 V.

Channels and Self-Aligned MBE Source–Drain Regrowth

We demonstrate In_0.53Ga_0.47As surface channel MOSFETs using a gate-last process and MBE source/drain (S/D) regrowth. The structure uses a sacrificial N+ InGaAs channel cap layer between the regrown S/D contact layer and the channel, which is removed in the channel region by a “digital” etch process incorporating UV ozone oxidation and surface stripping in dilute HCl. A device with 65 nm-L_g and 1.2 nm EOT shows 1.6 mS/μm peak transconductance at V_ds = 0.5 V and 120 mV/dec SS at V_ds = 0.05 V, while 535 nm-L_g devices show 95 mV/dec SS at at V_ds = 0.1 V.

Reduction of leakage current in In0.53Ga0.47As channel metal-oxide-semiconductor field-effect-transistors using AlAs0.56Sb0.44 confinement layers

As FETs are scaled, the dielectric and semiconductor channel thicknesses must be reduced to suppress short-channel effects. Even using fin field effect transistors (finFETs) and gate all around FETs (GAAFETs), [1],[2], whose electrostatic performance is excellent, at 4nm gate length the channel should be less than 2nm thick. To obtain high drive current per unit IC die area, the fin height should be many times the fin pitch, i.e. tens to hundreds of nm. Dry-etching a fin of few-nm width and > 100 nm height presents severe challenges in control of etch sidewall slope and in minimizing surface damage. Here we report an InGaAs finFET fabrication flow which form fins of sub-10nm width and 200 nm height. Fin width is controlled by atomic layer epitaxial (ALE) growth and by semiconductor selective crystallographic wet etching. We further demonstrate self-aligned source-drain regrowth in this process [3],[4]. This facilitates scaling of the source/drain pitch to small dimensions.

High transconductance surface channel In 0.53 Ga 0.47 As MOSFETs using MBE source-drain regrowth and surface digital etching

Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (R<inf>access</inf> &#60; 50 Ω-µ,¹ and D<inf>it</inf> &#60; 2 · 10¹² cm⁻² eV^−1,2 respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (L<inf>g</inf>), e.g. 116 nm at 32 nm L<inf>g</inf>,³ while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm L<inf>g</inf> In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at V<inf>ds</inf> = 1.25 V and V<inf>gs</inf> = 3 V and an R<inf>on</inf> = 341 ohm-µm. To our knowledge this is the lowest R<inf>on</inf> and smallest L<inf>g</inf> reported to date for In<inf>0.53</inf>Ga<inf>0.47</inf>As surface channel MOSFETs.⁴

Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy

We report a 30 GS/s sample-hold amplifier implemented in a combined InP HBT and Si CMOS heterogeneous integration technology. The high-speed signal path is entirely in InP, but droop in the sampled voltage arising from HBT bias currents is suppressed by an integrated CMOS feedback circuit. Under this closed-loop control, in hold mode, the droop rate of the single-ended outputs is reduced to 20 mV/ns. InP-CMOS interconnect parasitics are isolated from the high-speed signal path by isolation resistors and active bootstrapping. Given an 8 GHz input sampled at 32 GHz, the circuit shows input-referred P1dB and IIP3 of 0.5 dBm and 5.8 dBm, respectively. The total power consumption is 2.7 W and the chip area is 815 × 855 μm2.

60 nm gate length Al 2 O 3 / In 0.53 Ga 0.47 As gate-first MOSFETs using InAs raised source-drain regrowth

We describe a fabrication process which forms InGaAs fins with sub 10 nm thickness and 180 nm height. The process flow requires no semiconductor dry-etch, thereby avoiding surface damage arising from such processes. Instead, InGaAs fins are formed using nanometer controlled atomic layer epitaxial growth, using tertiarybutylarsine, upon InP sidewall which are eventually selectively etched. Such fins can serve as channels of field effect transistors, allowing excellent electrostatics and with potentially high operating current per fin.