Jeremy J. M. Law

Nitrogen-passivated dielectric/InGaAs interfaces with sub-nm equivalent oxide thickness and low interface trap densities

We report on the electrical characteristics of HfO2 and HfO2/Al2O3 gate dielectrics deposited on n-In0.53Ga0.47As by atomic layer deposition, after in-situ hydrogen or nitrogen plasma surface cleaning procedures, respectively. It is shown that alternating cycles of nitrogen plasma and trimethylaluminum prior to growth allow for highly scaled dielectrics with equivalent oxide thicknesses down to 0.6u2009nm and interface trap densities that are below 2.5u2009×u20091012u2009cm−2u2009eV−1 near midgap. It is shown that the benefits of the nitrogen plasma surface cleaning procedure are independent of the specific dielectric.

Al2O3 Growth on (100) In0.53Ga0.47As Initiated by Cyclic Trimethylaluminum and Hydrogen Plasma Exposures

The influence of hydrogen plasma treatment before atomic layer deposition of aluminum oxide on In0.53Ga0.47As is investigated. Experiments on untreated, trimethylaluminum-treated, hydrogen-plasma treated, and iterative hydrogen plasma/trimethylaluminum-treated samples are compared in the context of interface trap density, Dit. Through the conductance method, it was found that five cycles of two s, 20 mT, 100 W hydrogen plasma alternating with 40 msS of trimethylaluminum dose prior to dielectric growth resulted in a reduction of interface trap density (0.2 eV below the conduction band edge) from 4.6×1012 eV-1 cm-2 for untreated samples to 1.7×1012 eV-1 cm-2 for treated samples.

High performance raised source/drain InAs/In0.53Ga0.47As channel metal-oxide-semiconductor field-effect-transistors with reduced leakage using a vertical spacer

We demonstrate raised source/drain InAs/In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors incorporating a vertical spacer in the high-field region between the channel and the drain. The spacer significantly reduces off-state leakage at a high drain bias (VDS) without increasing the source/drain contact pitch. Subsequently, thinning the InAs layer within the channel further reduces the off-state leakage and subthreshold swing (SS). At ∼60u2009nm gate length and VDSu2009=u20090.5u2009V, devices with a 6u2009nm/3u2009nm InAs/In0.53Ga0.47As channel show 2.7 mS/μm peak transconductance (gm) and 125u2009mV/dec SS, while devices with a 4.5u2009nm/3u2009nm InAs/In0.53Ga0.47As channel show 2.4 mS/μm peak gm and 96u2009mV/dec SS.

III–V FET channel designs for high current densities and thin inversion layers

III–V FETs are being developed for potential application in 0.3–3 THz systems and VLSI. To increase bandwidth, we must increase the drive current I<inf>d</inf> = qn<inf>s</inf> v<inf>inj</inf>W<inf>g</inf> per unit gate width W<inf>g</inf>, requiring both high sheet carrier concentrations n<inf>s</inf> and high injection velocities v<inf>inj</inf>. Present III–V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, I<inf>d</inf> becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times.¹ The deep wavefunction also makes Γ -valley transport in low-m*materials unsuitable for < 22-nm gate length (L<inf>g</inf>) FETs. Yet, the L-valleys in many III–V materials² have very low transverse m<inf>t</inf> and very high longitudinal mass m<inf>1</inf>. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction^3,4. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ∼10–100 meV. Using combinations of Γ and L valleys, n<inf>s</inf> can be increased, m* kept low, and vertical confinement improved, key requirements for <20-nm L<inf>g</inf> III–V FETs.

Influence of gate metallization processes on the electrical characteristics of high-k/In0.53Ga0.47As interfaces

The influence of different gate metal deposition processes on the electrical characteristics of dielectric/III-V interfaces is investigated. Al2O3 and HfO2 dielectrics are grown on In0.53Ga0.47As channels and top metal electrodes are deposited by either thermal evaporation or electron beam deposition. It is shown that metal-oxide-semiconductor capacitors with electron beam evaporated electrodes exhibit substantially larger midgap interface trap densities than those with thermally evaporated electrodes. The damage caused by electron beam metallization can be mitigated by subsequent, long anneals in forming gas.

Simulation Study of Thin-Body Ballistic n-MOSFETs Involving Transport in Mixed

Transistor designs based on using mixed Γ-L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (τ) due to its single Γ valley.

\Gamma

III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the inversion layer depth, and increasing the channel 2-DEG density of states. We here describe both nm self-aligned fabrication processes and channel designs to address these scaling limits.

-L Valleys

We report enhancement-mode composite-channel (In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As) MOSFETs fabricated using a substitutional-gate process, with n⁺ relaxed InAs source-drain regions formed by regrowth by molecular beam epitaxy. A device with 70-nm gate length and 2-nm In_0.53Ga_0.47As/3.5-nm InAs/3-nm In_0.53Ga_0.47As channel showed a peak transconductance of greater than 0.76 mS/μm at <i>V</i>_ds = 0.4 V and showed <i>Id</i> = 0.5 mA/μm at <i>V</i>_ds = 0.4 V and <i>V</i>_gs - <i>V</i>_th = 0.7 V. The subthreshold swing at <i>V</i>_ds = 0.1 V was 130 mV/dec.

III-V MOSFETs: Scaling laws, scaling limits, fabrication processes

We compare the DC characteristics of planar In0.53Ga0.47As channel MOSFETs using AlAs0.56Sb0.44 barriers to similar MOSFETs using In0.52Al0.48As barriers. AlAs0.56Sb0.44, with ∼1.0u2009eV conduction-band offset to In0.53Ga0.47As, improves electron confinement within the channel. At gate lengths below 100u2009nm and VDSu2009=u20090.5u2009V, the MOSFETs with AlAs0.56Sb0.44 barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In0.52Al0.48As barrier to thermionic emission from the Nu2009+u2009In0.53Ga0.47As source over the In0.53Ga0.47As/In0.52Al0.48As heterointerface. A 56u2009nm gate length device with the AlAs0.56Sb0.44 barrier exhibits 1.96 mS/μm peak transconductance and SSu2009=u2009134u2009mV/dec at VDSu2009=u20090.5u2009V.

Substitutional-Gate MOSFETs With Composite

Because of the low effective mass, MOSFETs using In-rich (x>53%) InxGa1-xAs channels [1-5] exhibit high on-state current Ion at low drain bias (VDS=0.5 V). However, the small bandgap of high-indium InxGa1-xAs channels can lead to high off-state leakage Ioff due to band-to-band tunneling (BTBT) and impact ionization (I.I.). Earlier we had reported [1] that adding an unintentionally-doped (U.I.D.) InGaAs vertical spacer within the raised source/drain (S/D) of an InAs/InGaAs channel MOSFET substantially reduced Ioff. Here we compare the characteristics of FETs using a wide-bandgap U.I.D. InP vertical spacer to earlier results [1] using an InGaAs spacer, and to control devices using only a very thin spacer. We find that FETs using InP spacers have Ioff comparable to FETs using narrower-bandgap InGaAs spacers of similar thickness, suggesting that with the spacer, the observed Ioff at high VDS arises from BTBT or I.I. within the channel, and not within the high-field gate-drain spacer layer. Further, the wide-gap U.I.D. InP source spacer does not increase the threshold voltage Vth, suggesting that the gated potential barrier remains in the channel and not in the source spacer region. We also compare the on-state characteristics of FETs using InAs/InGaAs channels and an N+ InP S/D. Unlike the findings of [6], we do not observe improved Ion with the use of a wider-bandgap N+ source.