Doron Cohen Elias

Simulation Study of Thin-Body Ballistic n-MOSFETs Involving Transport in Mixed

Transistor designs based on using mixed Γ-L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (τ) due to its single Γ valley.

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While the growth of III-As and III-P semiconductors is well-established, and their transport properties well-understood, the performance of high-frequency and VLSI electron devices can still be substantially improved. Here we review design principles, experimental efforts, and intermediate results, in the development of nm and THz electron devices, including nm InAs/InGaAs planar MOSFETs and finFETs for VLSI, InGaAs/InP DHBTs for 0.1-1 THz wireless communications and imaging, and ~5nm InAs/InGaAs Schottky diodes for mid-IR mixing.

-L Valleys

Because of the low effective mass, MOSFETs using In-rich (x>53%) InxGa1-xAs channels [1-5] exhibit high on-state current Ion at low drain bias (VDS=0.5 V). However, the small bandgap of high-indium InxGa1-xAs channels can lead to high off-state leakage Ioff due to band-to-band tunneling (BTBT) and impact ionization (I.I.). Earlier we had reported [1] that adding an unintentionally-doped (U.I.D.) InGaAs vertical spacer within the raised source/drain (S/D) of an InAs/InGaAs channel MOSFET substantially reduced Ioff. Here we compare the characteristics of FETs using a wide-bandgap U.I.D. InP vertical spacer to earlier results [1] using an InGaAs spacer, and to control devices using only a very thin spacer. We find that FETs using InP spacers have Ioff comparable to FETs using narrower-bandgap InGaAs spacers of similar thickness, suggesting that with the spacer, the observed Ioff at high VDS arises from BTBT or I.I. within the channel, and not within the high-field gate-drain spacer layer. Further, the wide-gap U.I.D. InP source spacer does not increase the threshold voltage Vth, suggesting that the gated potential barrier remains in the channel and not in the source spacer region. We also compare the on-state characteristics of FETs using InAs/InGaAs channels and an N+ InP S/D. Unlike the findings of [6], we do not observe improved Ion with the use of a wider-bandgap N+ source.

Nanometer InP electron devices for VLSI and THz applications

We demonstrate In_0.53Ga_0.47As surface channel MOSFETs using a gate-last process and MBE source/drain (S/D) regrowth. The structure uses a sacrificial N+ InGaAs channel cap layer between the regrown S/D contact layer and the channel, which is removed in the channel region by a “digital” etch process incorporating UV ozone oxidation and surface stripping in dilute HCl. A device with 65 nm-L_g and 1.2 nm EOT shows 1.6 mS/μm peak transconductance at V_ds = 0.5 V and 120 mV/dec SS at V_ds = 0.05 V, while 535 nm-L_g devices show 95 mV/dec SS at at V_ds = 0.1 V.

Influence of InP source/drain layers upon the DC characteristics of InAs/InGaAs MOSFETs

We describe a fabrication process which forms InGaAs fins with sub 10 nm thickness and 180 nm height. The process flow requires no semiconductor dry-etch, thereby avoiding surface damage arising from such processes. Instead, InGaAs fins are formed using nanometer controlled atomic layer epitaxial growth, using tertiarybutylarsine, upon InP sidewall which are eventually selectively etched. Such fins can serve as channels of field effect transistors, allowing excellent electrostatics and with potentially high operating current per fin.

High transconductance surface channel In 0.53 Ga 0.47 As MOSFETs using MBE source-drain regrowth and surface digital etching

Given low interface trap densities and low access resistances, InGaAs MOSFETs can provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT), and are thus strong candidates for use in VLSI.¹ Transconductance as high as 2.1 mS/μm (V_ds=0.5 V) with 115 mV/decade (V_ds=0.5 V) subthreshold swing has been reported² in planar III-V MOSFETs using a gate recess etch through the N+ InGaAs contact layer. It remains to be established whether the necessary etch depth control can be obtained at VLSI integration scales and 10-20 nm gate lengths. Using self-aligned regrowth of the N+ source and drain, III-V MOSFETs can be fabricated without requiring this gate recess etch;³ 1.9 mS/μm (V_d =1 V) with 116 mV/decade (V_ds=0.05 V) subthreshold swing was reported in a 55 nm L_g InGaAs MOSFET with MOCVD source-drain regrowth.⁴ Note that no post-regrowth etching of the channel surface is reported in (4). We have recently found⁵ that InGaAs MOSFETs using MBE source-drain regrowth, subthreshold swing and transconductance are substantially improved by removing a 5 nm N+ InGaAs channel cap post-regrowth and immediately prior to gate dielectric deposition, suggesting damage to the channel surface during regrowth. Here, we report similar findings for MOCVD regrowth. We fabricated 65 nm L_g In₀.₅₃Ga_0.47As surface-channel MOSFETs in a gate-last process with self-aligned raised InGaAs S/D access regions formed by MOCVD regrowth. Removal of ~ 2.4 nm of the channel surface by digital etching improved the transconductance from 1.1 to 1.58 mS/μm (65 nm L_g V_d=0.5 V), and reduced the subthreshold swing from 326 to 110 mV/dec (1 μm L_g, V_ds=0.05 V). These results suggest that substantial surface damage arises, and must be addressed, in MOCVD regrowth III-V MOSFET processes.

Formation of InGaAs fins by atomic layer epitaxy on InP sidewalls

As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage VDD. With thermally-activated, FETs, the off-state leakage Ioff and target on-current Ion then determine the minimum feasible VDD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high Ion at low Ioff and low VDD is challenging. Subthreshold logic [2] operates at lowVDD, but is slow because of low Ion. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed VDD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing VDD to ~300mV while maintaining large Ion per unit IC die area.

Performance impact of post-regrowth channel etching on InGaAs MOSFETs having MOCVD source-drain regrowth

In large-scale digital systems, propagation delay and power consumption of the interconnects are vastly larger than that of the transistors themselves [1,2]. Reduced power consumption, and increased capacity is required for interconnects, whether on-chip, between circuit boards, or within large data centers. Here we will consider coherent optical interconnects for high-capacity, sub-km links within data centers. At the other extreme of interconnect length, we will also briefly consider alternative approaches for reduced CV2/2 switching energy of VLSI interconnects.

Prospects for high-aspect-ratio FinFETs in low-power logic

Recently, InAs or In-rich InGaAs (In>53%) has been widely studied as the channel material for III-V FETs due to its superior electron transport properties over In_0.53Ga_0.47As. These materials provide excellent on-state characteristics, e.g. >2.5 mS/μm peak transconductanc (g_m) at V_DS=0.5 V [1-3]. The narrow bandgap in these materials, however, causes band-to-band tunneling (BTBT) in the high drain-field region even at relatively low supply voltage of 0.5 V, thus resulting in high leakage at the off-state [1][3]. In our previous work, in order to address this issue, we incorporated a vertical spacer between the channel and N+ source/drain (S/D) to accommodate the depletion region near the channel-drain junction. The spacer significantly improved off-state characteristics such as off-state leakage, drain-induced barrier lowering (DIBL), and subthreshold swing (SS) without increasing the device footprint [3], [4]. In this work, by adopting a ~4 nm-thick In_0.53Ga_0.47As channel instead of a thick InAs channel, we have further improved the off-state characteristics at high V_DS and achieved 81 mV/dec. minimum subthreshold swing (SS_min) for a 35 nm-L_g device at V_DS=0.5 V and 385 μA/μm on-current (I_on) at 100 nA/μm off-current (I_off) and V_DD=0.5 V, which are the best SS_min and I_on from all reported In_0.53Ga_0.47As channel FETs.

Phase-locked coherent optical interconnects for data links

We report high transconductance MOSFETs with scaled dielectric (1.2 nm EOT) fabricated using a substitutional-gate process with MBE source/drain regrowth. A 50 nm-L_g and 1.2 nm EOT device shows 0.8 mA/μm on-current at V_gs-V_th = 0.8 V and V_ds = 0.5 V and 1.0 mS/μm peak transconductance at V_ds = 0.5 V which are 25% and 40% higher than those of a 1.65 nm EOT control device, respectively. Transmission line method (TLM) measurements indicate 0.8 Ohm-μm² metal-semiconductor contact resistivity and 18 Ohm sheet resistance of the regrown N+ source-drain contact layer.