Paul Leventis

The Stratix II logic and routing architecture

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The stratixπ routing and logic architecture

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

Generating highly-routable sparse crossbars for PLDs

A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to accurately compute the percentage of random test vectors that can be routed. The construction method attempts to maximize the spread of the switch locations, such that any given subset of input wires can connect to as many output wires as possible. Based on Halls Theorem, we argue that this increases the likelihood of routing. The hardest test vectors to route are those which attempt to use all of the crossbar outputs. Results in this paper show that area-efficient sparse crossbars can be constructed by providing more outputs than required and a sufficient number of switches. In a few specific case studies, it is shown that sparse crossbars with about 90% fewer switches than a full crossbar can be constructed, and these crossbars are capable of routing over 95% of randomly chosen routing vectors. In one case, a new switch matrix which can replace the one in the Altera FLEX8000 family is shown. This new switch matrix uses approximately 14% more transistors, yet can increase the routability of the most difficult test vectors from 1% to over 96%.

MAX II: A low-cost, high-performance LUT-based CPLD

This paper describes the MAX II CPLD architecture. Departing from traditional CPLD product-term logic elements and global routing, it instead employs FPGA-like look-up tables and channel-based routing. It integrates a flash memory for configuration and a voltage regulator for core power flexibility, and delivers 2.9/spl times/ higher logic density, 2.2/spl times/ greater performance, and consumes >15/spl times/ less power in 1/6 the die size of its predecessor, the MAX 7000A.

Does IC design have a future in the clouds

Cloud computing is used to describe a collection of (remote) data centers (the hardware and the software) and applications delivered from them as a service (SaaS, Software as a Service). Its success is driven by the cost-effective on-demand availability of large, scalable amounts of computing resources. The cloud has become an established paradigm for many enterprise and consumer applications such as email, web servers, productivity applications, customer relationship management, etc. However, in IC design its success is still limited.This panel will discuss the real and perceived hurdles that currently prevent a broad adoption of cloud computing in IC design, and several scenarios on how this could happen.

Cyclone /spl trade/: a low-cost, high-performance FPGA

This paper describes the Altera Cyclone/spl trade/ FPGA, an architecture specifically designed for low-cost, high-volume applications. An optimized routing architecture, simplified I/O structure, and carefully selected features combine to yield a 57% die size reduction relative to a Stratix/spl trade/ device of similar logic density, with a 7% reduction in performance.