Cameron McClintock

The Stratix II logic and routing architecture

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The stratixπ routing and logic architecture

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

A high density embedded array programmable logic architecture

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.

Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process

A global interconnect architecture with dual granularity demonstrates considerable migration capability from the original product on 0.8Μ two layer metal process by reducing die size to one third while nearly doubling system frequency when transferred to a 0.5Μ three layer metal process.

A low power programmable logic device reconfigurable for 3.3 V or 5.0 V operation during and after fabrication

A programmable logic device which is reconfigurable to operate at either a 3.3 V or 5.0 V supply specification has been fabricated. On-chip circuitry is dynamically adjusted for 3.3 V or 5.0 V operation. The voltage supply configuration can be changed after fabrication by opening a fuse or writing into a selection register. The device consumes less than 500 /spl mu/W of power at 3.3 volts.<<ETX>>