Richard G. Cliff

The Stratix II logic and routing architecture

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The stratixπ routing and logic architecture

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

The implementation of hardware subroutines on field programmable gate arrays

The dynamically reconfigurable Plessey ERA (electrically reconfigurable array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces the concept of the hardware subroutine. The ERA requires 2.5 times less data per equivalent gate as compared to the established industry standard devices. In addition, loading the data in parallel bytes at clock speeds up to 25 MHz reduces the time taken for the complete configuration of a 10000 equivalent gate array to less than 140 mu s.<<ETX>>

A dual granularity and globally interconnected architecture for a programmable logic device

A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity approach and a global interconnect strategy. The dual granularity and global interconnect approach has succeeded in supporting both short nets and long nets for maximum performance.

A high density embedded array programmable logic architecture

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.

A next generation architecture optimized for high density system level integration

Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system. This new architecture will support a family of devices exceeding 2 million gates in density. Density and speed improvements are achieved through an enhanced hierarchical routing structure.

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES

A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.

A silicon efficient FLEX 6000 programmable logic architecture

An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routing and high cost efficiency in the interconnect, logic array blocks, and I/O elements. Other architecture features include built-in low skew clock, programmable output slew rate control, PCI compliant I/O, JTAG boundary scan, individual output enable for each I/O pin, and in-circuit configuration. The first member of the family is currently available with 16000 gate density and 125 MHz performance for 16-bit counter application.

Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process

A global interconnect architecture with dual granularity demonstrates considerable migration capability from the original product on 0.8Μ two layer metal process by reducing die size to one third while nearly doubling system frequency when transferred to a 0.5Μ three layer metal process.