Anelise Kologeski

Adaptive router architecture based on traffic behavior observability

A Network-on-Chip with large FIFO size ensures performance during the execution of different traffic flow, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers to reach higher throughput incurs in extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of an adaptive router with a mechanism that, using a flow sensor, verifies during run time the behavior of the data traffic. From the observability of the data flow, the system uses a control equation that adapts itself to provide an appropriate buffer depth for each channel to sustain performance with minimum power dissipation. As applications show different traffic behavior at run-time, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was 75% lower and throughput was increased 4.6 times to Xbox application, for the same buffer depth. Moreover, the adaptive router allows up to 28% power savings, while maintain the same performance of the equivalent homogeneous router.

Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links

A strategy to handle multiple defects in the No Clinks with almost no impact on the communication delay is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link, and with multiple faulty links. The proposed technique uses information from test phase to map the application and to configure fault-tolerant features along the NoC links. Results from an application remapped in the NoC show that the communication delay is almost unaffected, with minimal impact and overhead when compared to a fault-free system. We also show that our proposal has a variable impact in performance while traditional fault-tolerant solution like Hamming Code has a constant impact. Besides our proposal can save among 15% to100% the energy when compared Hamming Code.

A NOC closed-loop performance monitor and adapter

In a NoC, the amount of buffers allocated to each communication channel has a significant impact on performance and power consumption. Moreover, since there will be changes in the application communication pattern, or even because a new application is loaded in a SoC, a design based on the worst case scenario will probably either oversize buffers, with obvious power implications, or the performance will be compromised, since not enough buffers will be available. A runtime mechanism is required to automatically adapt the buffer size as a function of the communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router. The runtime mechanism is able to monitor the traffic behavior and to control, for each channel, the required buffer size of the adaptive router. Besides, as the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. This way, a technique to isolate faulty buffers is also presented. Experimental results using the proposed architecture have shown that, in the absence of faults, the latency has been decreased by 80%, and throughput has been increased by 45%, in the worst case. In the presence of faults, the proposed architecture was able to sustain the same performance of the equivalent homogeneous router, but with up to 25% power savings.

Two-levels of adaptive buffer for virtual channel router in NoCs

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. Moreover, routers with virtual channels have larger buffer sizes and more complex control, increasing the total costs. The situation worsens whenever the application changes its communication pattern, i.e., when a portable phone downloads a new service. In this paper we propose the use of a two-level adaptive buffer for a virtual channel router, where the buffers units and the virtual channels are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. With the proposed architecture the buffer and virtual channels in the input channels of the routers can be adapted at run time. The adaptive virtual channel router decreases the latency in the worst case by 10%, and a reduction of 80% in the best case is achieved when compared to previous works.

Performance exploration of partially connected 3D NoCs under manufacturing variability

Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

Adaptive approach to tolerate multiple faulty links in Network-on-Chip

A novel approach to handle multiple defects in the NoC links is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link and with multiple faulty links. The proposed technique uses information from test to know where and when fault-tolerant features must be turned on. Comparisons with popular solutions based on EDAC show that the proposed method can provide a faster communication, while coping with multiple defects in the link without the need of extra wires. In addition, the adaptive approach saves energy because it is used only when required.

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip

The design of 3D circuits have been motivated by the need of decreasing the wire length in System-on-Chip (SoC) composed of more and more high number of processing elements. In general, advantages such as aiding the test methodology and increasing fault tolerance can be observed. However, the development of 3D circuits is not trivial, and there are still challenges in the manufacture process. The objective of this work is to address a low cost solution to improve the yield in TSVs, combining fault tolerance in horizontal interconnections, in order to minimize the fault susceptibility in 3D-NoCs. Comparisons among different serialization levels have been developed to show the advantages.

ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections

The use of embedded fault-tolerant mechanisms in Network-on-Chips (NoCs) has become essential to ensure connectivity in the presence of massive defects, and consequently improving the yield. According to the number of defects and their location in NoC, the fault tolerant techniques can be very expensive in terms of area, performance and energy overhead. The use of testing and diagnosis can help to minimize costs associated to embedded fault tolerant mechanisms because they can be adapted to work only at the defect regions. Our fault tolerant strategy is based on adaptive routing and data splitting to cope with massive defects in NoC interconnections. The combination of these two techniques adds significant improvements in reliability and energy efficiency. Experimental results with random massive interconnection faults have shown that our proposal can still sustain 100% of connectivity with 60% of defected wires. The energy penalty may vary from only 5 to up to 40% as a function of the number of faulty interconnections, which is much less overhead compared to techniques as hamming code.

Monitor-adapter coupling for NOC performance tuning

The amount of buffers allocated to each NoC channel has a significant performance and power consumption impact. Moreover, when a NoC-based application could present changes in the communication pattern, or when a new application could be loaded in a SoC, a NoC design based on the worst case scenario probably will present oversize buffers. Besides, it will cause obvious power implications, or the performance will be compromised, since not enough buffers will be used. A runtime mechanism is required to automatically adapt the buffer size as a function of the actual communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router, which is able to monitor the traffic behavior, and change the buffer depth of each channel at runtime. Besides, the dynamic configuration of the buffer depth is done without any pause or interruption in the system. As applications show different traffic behavior at runtime, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was approximately 80% lower and throughput was increased 2 times, on average, for the same buffer depth. Moreover, the adaptive router allows up to 30% power savings, while maintain the same performance of the equivalent homogeneous router.

Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario

The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). However, many challenges during the 3D manufacturing phase are making the circuits more vulnerable and prone to failure. This work investigates the impact on latency in 3D NoCs under multiple faulty TSVs and it proposes a technique to ensure the connectivity of the NoC under multiple faults scenario. A fault model was proposed with four different configurations to distribute multiple faulty TSVs in the 3D NoC. Three different fault tolerant scenarios were explored: the first is the original routing algorithm called Elevated-First used to avoid faulty vertical connections. The second and third scenarios are our new designs based on the use of dynamic monitors to observe the flow through the paths, in order to be able to select best alternative paths under multiple faults. Fault injection results show that it is possible to reduce the latency impact from 1x to 10x in the best case configuration by use the proposed solutions.