Caroline Concatto

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router

As the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. However, faults can affect the routers services, thus compromising the communication integrity and the whole operation of the system. This work proposes the simultaneous use of Reconfiguration, Hamming Code and Triple Modular Redundancy (TMR) to ensure fault tolerance in the FIFOs and links of the network-on-chips (NoCs). The proposed router can dynamically stop using faulty buffers and, to sustain performance, borrow other buffer units from its neighbor channels whenever necessary. The Hamming Code protects the data in the links against a fault in a wire, while TMR is used to protect the control of the FIFO. The new router increases the reliability in 63% and shows low latency and power when compared to the original router. The HW overhead is 77% more gates, used to improve the yield and the system lifetime in comparison to the usage of the reconfigurable router just for performance increase in the NoC.

Adaptive router architecture based on traffic behavior observability

A Network-on-Chip with large FIFO size ensures performance during the execution of different traffic flow, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers to reach higher throughput incurs in extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of an adaptive router with a mechanism that, using a flow sensor, verifies during run time the behavior of the data traffic. From the observability of the data flow, the system uses a control equation that adapts itself to provide an appropriate buffer depth for each channel to sustain performance with minimum power dissipation. As applications show different traffic behavior at run-time, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was 75% lower and throughput was increased 4.6 times to Xbox application, for the same buffer depth. Moreover, the adaptive router allows up to 28% power savings, while maintain the same performance of the equivalent homogeneous router.

Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links

A strategy to handle multiple defects in the No Clinks with almost no impact on the communication delay is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link, and with multiple faulty links. The proposed technique uses information from test phase to map the application and to configure fault-tolerant features along the NoC links. Results from an application remapped in the NoC show that the communication delay is almost unaffected, with minimal impact and overhead when compared to a fault-free system. We also show that our proposal has a variable impact in performance while traditional fault-tolerant solution like Hamming Code has a constant impact. Besides our proposal can save among 15% to100% the energy when compared Hamming Code.

A NOC closed-loop performance monitor and adapter

In a NoC, the amount of buffers allocated to each communication channel has a significant impact on performance and power consumption. Moreover, since there will be changes in the application communication pattern, or even because a new application is loaded in a SoC, a design based on the worst case scenario will probably either oversize buffers, with obvious power implications, or the performance will be compromised, since not enough buffers will be available. A runtime mechanism is required to automatically adapt the buffer size as a function of the communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router. The runtime mechanism is able to monitor the traffic behavior and to control, for each channel, the required buffer size of the adaptive router. Besides, as the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. This way, a technique to isolate faulty buffers is also presented. Experimental results using the proposed architecture have shown that, in the absence of faults, the latency has been decreased by 80%, and throughput has been increased by 45%, in the worst case. In the presence of faults, the proposed architecture was able to sustain the same performance of the equivalent homogeneous router, but with up to 25% power savings.

Two-levels of adaptive buffer for virtual channel router in NoCs

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. Moreover, routers with virtual channels have larger buffer sizes and more complex control, increasing the total costs. The situation worsens whenever the application changes its communication pattern, i.e., when a portable phone downloads a new service. In this paper we propose the use of a two-level adaptive buffer for a virtual channel router, where the buffers units and the virtual channels are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. With the proposed architecture the buffer and virtual channels in the input channels of the routers can be adapted at run time. The adaptive virtual channel router decreases the latency in the worst case by 10%, and a reduction of 80% in the best case is achieved when compared to previous works.

Adaptive approach to tolerate multiple faulty links in Network-on-Chip

A novel approach to handle multiple defects in the NoC links is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link and with multiple faulty links. The proposed technique uses information from test to know where and when fault-tolerant features must be turned on. Comparisons with popular solutions based on EDAC show that the proposed method can provide a faster communication, while coping with multiple defects in the link without the need of extra wires. In addition, the adaptive approach saves energy because it is used only when required.

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip

The design of 3D circuits have been motivated by the need of decreasing the wire length in System-on-Chip (SoC) composed of more and more high number of processing elements. In general, advantages such as aiding the test methodology and increasing fault tolerance can be observed. However, the development of 3D circuits is not trivial, and there are still challenges in the manufacture process. The objective of this work is to address a low cost solution to improve the yield in TSVs, combining fault tolerance in horizontal interconnections, in order to minimize the fault susceptibility in 3D-NoCs. Comparisons among different serialization levels have been developed to show the advantages.

ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections

The use of embedded fault-tolerant mechanisms in Network-on-Chips (NoCs) has become essential to ensure connectivity in the presence of massive defects, and consequently improving the yield. According to the number of defects and their location in NoC, the fault tolerant techniques can be very expensive in terms of area, performance and energy overhead. The use of testing and diagnosis can help to minimize costs associated to embedded fault tolerant mechanisms because they can be adapted to work only at the defect regions. Our fault tolerant strategy is based on adaptive routing and data splitting to cope with massive defects in NoC interconnections. The combination of these two techniques adds significant improvements in reliability and energy efficiency. Experimental results with random massive interconnection faults have shown that our proposal can still sustain 100% of connectivity with 60% of defected wires. The energy penalty may vary from only 5 to up to 40% as a function of the number of faulty interconnections, which is much less overhead compared to techniques as hamming code.

Improving the yield of NoC-based systems through fault diagnosis and adaptive routing

We propose an effective and low cost method to increase the yield and the lifetime of torus NoCs. The method consists in detecting and diagnosing NoC interconnect faults using BIST structures and activating alternative paths for the faulty links. Alternative paths use the inherent redundancy of the torus topology, thus leading to minimal performance, area, and power overhead. We assume an extended interconnect fault model comprising stuck-at and pairwise shorts within a single link or between any two links in the network. Experimental results for a 3x3 NoC show that the proposed approach can correctly diagnose 93% of all possible interconnect faults and can mitigate 42% of those faults (representing 94.4% of the solvable faults) with a worst case performance penalty of 8% and 1% of area overhead. We also demonstrate the scalability of the method by presenting its application to larger NoCs.