Aneta Prijić

Thermal Energy Harvesting Wireless Sensor Node in Aluminum Core PCB Technology

This paper reports the design of a self-powered telemetric wireless sensor node for temperature measurement. The device is realized with a conventional off-the-shelf thermoelectric generator as a power source. It is sandwiched between two aluminum core printed circuit boards (PCBs). One board is exposed to the heat source and has the role of a heat collector, whereas another one with the mounted low profile heatsink acts as a heat spreader. Electronic components of the node are placed on the inner surfaces of the boards. Implemented step-up circuitry is accommodated to achieve stabile cold boot of the node at a low temperature difference between its hot side and ambient (less than 15 °C), even when it is in thermally inefficient position. Operational autonomy of the node in the absence of the heat source is extended by 30% comparing with the common step-up circuitry implementation. The aluminum core PCBs provide node simplicity and compactness, with small overall dimensions.

Dependence of Static Dielectric Constant of Silicon on Resistivity at Room Temperature

The static dielectric constant of the heavily doped silicon at room temperature is considered. By using phosphorus as an example, the existing expression for the static dielectric constant at low temperatures is recast into a form suitable for the application at room temperature. This is done by taking into account the contribution of non-ionized impurities at room temperature to the static dielectric constant behavior.

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz <f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔV T can be reduced to a quarter of ΔV T found after the static NBT stress.

On the Recoverable and Permanent Components of NBTI in p-Channel Power VDMOSFETs

This paper introduces a new experimental approach allowing to investigate the recoverable and permanent components in commercial p-channel power VDMOSFETs subjected to negative bias temperature (NBT) stressing. In many applications, devices can be used in multiple modes, which include application of static or pulsed gate voltages at different stages of device operation. Accordingly, we have investigated stress-induced degradation in the cases where the static stress was followed by the pulsed NBT stress conditions and vice versa. The results are discussed in terms of the mechanisms responsible for the buildup of oxide charge and interface traps. It has been shown that the differences in the permanent components of the oxide charge and interface traps between devices exposed to static stress followed by pulsed NBT stress and those exposed only to static NBT stress tend to decrease during the pulsed stress as the duty cycle increases but cannot be completely removed.

Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

In this study, which is aimed at assessing a possible relationship between the recoverable and permanent components of negative bias temperature instability (NBTI) degradation, we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs (vertical double diffused MOSFETs) stressed under particular pulsed bias conditions by varying the pulse on-time while keeping the off-time constant and vice versa. The stress-induced threshold voltage shifts are found to be practically independent of duty cycle when the pulse on-time is kept short or the off-time is kept long, and are found to start increasing with duty cycle only when the on-time is increased or the off-time is decreased beyond specific values. These results, which are discussed in terms of dynamic recovery effects and the mechanisms leading to NBTI degradation, point to the existence of an important correlation between the recoverable and permanent components of degradation.

Recoverable and permanent components of V T shift in pulsed NBT stressed p-channel power VDMOSFETs

In this study we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs under both static and pulsed bias stress conditions. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. Recoverable and permanent components of threshold voltage shift in pulsed negative bias temperature stressed devices are investigated in detail. The existence of characteristic time constant (25 μs), related to a complete removal of the recoverable component of degradation, is clearly shown. Finally, the average value of permanent component of VT shift induced by a single stress pulse is determined (1.34 × 10-10 V).

Negative Bias Temperature Instability in Thick Gate Oxides for Power MOS Transistors

Vast majority of recent extensive investigations of Negative Bias Temperature Instability (NBT) have been focused to the related phenomena in ultrathin gate dielectric layers of SiO2, SiON, and high-k materials. However, even though the gate oxides in nanometer scale technologies have been continuously thinned down, the interest in thick oxides has not ceased owing to widespread use of MOS technologies for the realization of power devices. Power MOSFETs are widely used as fast switching devices in home appliances and automotive, industrial, and military electronics. In a number of applications, these devices are routinely operated in the harsh environment and at high current and voltage levels, which lead to self-heating and/or increased fields, and thus favor NBTI. Accordingly, NBTI could be critical for reliable operation of power MOSFETs even though they have ultra-thick gate oxides. Our research over the past few years has been focused to degradation mechanisms in p-channel power Vertical Double-Diffused MOSFETs (VDMOSFETs) subjected to NBT stressing, including effects found during the post-stress annealing under the low gate bias and during the sequence of several NBT stress and low gate bias annealing steps. NBTI in n-channel power VDMOSFETs has been investigated as well. This chapter is aimed at revealing the main features of NBTI in thick gate oxides for power MOSFETs and reviews the work mentioned above with suitable reference to other published work. Peculiarities associated with NBTI in thick oxides, such as the unusual post-stress generation of interface traps and rarely observed remarkable instability in n-channel devices are particularly addressed.

An Electromechanical Approach to a Printed Circuit Board Design Course

This paper describes a printed circuit board (PCB) design course based on electromechanical workflow. The course relies on the premise that a PCB is an integral component of any electronic apparatus, along with its other electromechanical and mechanical components. To emphasize this to students, electrical and mechanical computer-aided design tools are used in synergy. The course content is described in detail, and the design workflow is illustrated, using a project to design a data acquisition instrument as an example.

A method for negative bias temperature instability (NBTI) measurements on power VDMOS transistors

A method suitable for performing NBTI measurements on power p-channel VDMOS transistors is described. A practical implementation using simple boosting circuit for obtaining required gate stress voltage and sweep I–V measurements for the threshold voltage shift determination is presented. Experimental results are discussed in terms of the time necessary to perform interim measurements during NBTI tests. It is shown that the measurements could be done fast enough to capture part of the dynamic recovery effect in these devices, which is important for the lifetime prediction.

NBTI related degradation and lifetime estimation in p-channel power VDMOSFETs under the static and pulsed NBT stress conditions

Abstract The effects of static and pulsed NBT stressing on threshold voltage in p-channel power VDMOSFETs are analysed, and the results are compared in terms of the effects on device lifetime. The results obtained by both “1/VG” and “1/T” models, which are used for extrapolation to normal operation voltages and temperatures, respectively, indicate the device lifetime could be much longer under the pulsed stress conditions than under the static ones. It is also shown that lifetime tends to increase with decreasing the duty cycle of pulsed stress voltage applied.