Danijel Dankovic

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.

Effects of electrical stressing in power VDMOSFETs

Abstract The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon Si o defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps Si o + to interface-trap precursors Sis–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects Si o Si o is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Sis–H with the charged oxide traps Si o + Si o and H+ ions are proposed to be responsible for interface trap buildup.

NBT stress-induced degradation and lifetime estimation in p-channel power VDMOSFETs

Abstract Threshold voltage shifts found in commercial p-channel power VDMOSFETs during the NBT stressing are fitted using stretched exponential equation in order to estimate the device lifetime, as well as to discuss the impacts of stress conditions, choice of extrapolation parameters, and extrapolation model. Excellent agreement between the stretched exponential fit and experimental data found in later stress phases allows for an accurate estimation of device lifetime for the lowest stress voltage applied, which justifies the use of stretched exponential or some other suitable fit. The realistic failure criterion for devices and experimental conditions used in our study is found to fall in the 100–150 mV range. The lifetime estimates are found to strongly depend on the model used for extrapolation to normal operating conditions. The 1/ V G model is shown to provide much faster output since it appears to allow the use of higher stress voltages while still yielding rather accurate lifetime estimates.

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs have been investigated to get better insight into the NBTI phenomena. Negative bias annealing does not affect stress-induced degradation significantly, whereas either zero or positive bias annealing removes the portion of stress-induced oxide-trapped charge while creating additional interface traps. The removable component of stress-induced oxide-trapped charge is found to decrease, and influence of external bias on annealing phenomena weakens with duration of preceding stressing, suggesting that extended stress moves the trapped charge to energetically deeper oxide traps, which are more difficult to anneal.

Negative bias temperature instability in n-channel power VDMOSFETs.

Abstract Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal V T shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall V T instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model.

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs.

Abstract The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO2/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal-oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz <f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔV T can be reduced to a quarter of ΔV T found after the static NBT stress.

Impact of Negative Bias Temperature Instabilities on Lifetime in p-channel Power VDMOSFETs

Negative bias temperature instabilities (NBTI) are commonly observed in p-channel metal-oxide-semiconductor (MOS) devices when exposed to negative gate voltages at elevated temperatures. We present a brief overview of NBT stress- induced threshold voltage instabilities in p-channel vertical double-diffused MOS field-effect transistors (VDMOSFETs). NBT stress-induced threshold voltage shifts are fitted using different models to estimate the device lifetime and to discuss the impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection. The stretched exponential equation is found to provide excellent fit to experimental data for the later stress phases and thus allows an accurate estimation of device lifetime for the lowest stress voltage applied, which justifies the use of this or some other suitable fitting equation. The realistic failure criterion for devices and experimental conditions used in our studies is found to fall in the 100 - 150 mV range. The lifetime estimates are found to strongly depend on the model used for extrapolation to normal operating conditions. The 1/VG model is shown to provide much faster output since it appears to allow the use of higher stress voltages while still yielding rather accurate lifetime estimates. Intermittent annealing does not seem to have any significant impact on device lifetime.

Effects of gate bias stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analyzed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunneling from neutral oxide traps associated with trivalent silicon ≡Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunneling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunneling from the silicon valence band to oxygen vacancy defects ≡Sio / Sio≡ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ≡Sis−Η with the charged oxide traps ≡Sio+ Sio≡ and H+ ions are proposed to be responsible for interface trap buildup.