S. Djoric-Veljkovic

Modeling Radiation-Induced Mobility Degradation in MOSFETs

This paper analyses the relationship between two forms of channel-carrier mobility models, both of them employing linear combinations of oxide- and interface-trapped charge densities. The original form of this model is based on the overall densities of oxide- and interface-trapped charge, while another form of this model uses the radiation-induced charge densities as a convenient way of expressing the radiation-induced mobility degradation. It is shown that the radiation-degradation form of the mobility model employs coefficients which are dependent on both the bulk and the initial mobility values. This fact is very important in terms of proper analysis of experimental results on radiation-induced mobility degradation.

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal-oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.

Effects of burn-in stressing on radiation response of power VDMOSFETs

Abstract The effects of pre-irradiation burn-in stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of power MOSFETs. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects. The buildup of oxide-trapped charge appeared to be almost independent of device pre-irradiation stress, while the buildup of interface traps was somewhat less pronounced in stressed devices. Passivation of interface-trap precursors due to diffusion of hydrogen related species (originating either from package inside or gate oxide adjacent structures) from the bulk of the oxide towards the interface has been proposed as a mechanism responsible for the suppressed interface-trap buildup in pre-irradiation stressed devices.

Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

In this study, which is aimed at assessing a possible relationship between the recoverable and permanent components of negative bias temperature instability (NBTI) degradation, we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs (vertical double diffused MOSFETs) stressed under particular pulsed bias conditions by varying the pulse on-time while keeping the off-time constant and vice versa. The stress-induced threshold voltage shifts are found to be practically independent of duty cycle when the pulse on-time is kept short or the off-time is kept long, and are found to start increasing with duty cycle only when the on-time is increased or the off-time is decreased beyond specific values. These results, which are discussed in terms of dynamic recovery effects and the mechanisms leading to NBTI degradation, point to the existence of an important correlation between the recoverable and permanent components of degradation.

Negative Bias Temperature Instability in Thick Gate Oxides for Power MOS Transistors

Vast majority of recent extensive investigations of Negative Bias Temperature Instability (NBT) have been focused to the related phenomena in ultrathin gate dielectric layers of SiO2, SiON, and high-k materials. However, even though the gate oxides in nanometer scale technologies have been continuously thinned down, the interest in thick oxides has not ceased owing to widespread use of MOS technologies for the realization of power devices. Power MOSFETs are widely used as fast switching devices in home appliances and automotive, industrial, and military electronics. In a number of applications, these devices are routinely operated in the harsh environment and at high current and voltage levels, which lead to self-heating and/or increased fields, and thus favor NBTI. Accordingly, NBTI could be critical for reliable operation of power MOSFETs even though they have ultra-thick gate oxides. Our research over the past few years has been focused to degradation mechanisms in p-channel power Vertical Double-Diffused MOSFETs (VDMOSFETs) subjected to NBT stressing, including effects found during the post-stress annealing under the low gate bias and during the sequence of several NBT stress and low gate bias annealing steps. NBTI in n-channel power VDMOSFETs has been investigated as well. This chapter is aimed at revealing the main features of NBTI in thick gate oxides for power MOSFETs and reviews the work mentioned above with suitable reference to other published work. Peculiarities associated with NBTI in thick oxides, such as the unusual post-stress generation of interface traps and rarely observed remarkable instability in n-channel devices are particularly addressed.

New approach in estimating the lifetime in NBT stressed P-channel power VDMOSFETs

A brief overview of NBT stress-induced threshold voltage instabilities in p-channel power vertical double- diffused MOS field-effect transistors (VDMOSFETs) is presented. New approach in estimating the lifetime in NBT stressed p-channel power VDMOSFETs is proposed. The creation of lifetime surface for operating area, which can be useful for determination of device lifetime, operating temperature or operating bias, is demonstrated as well.

Lifetime Estimation in NBT Stressed P-Channel Power VDMOSFETs

Threshold voltage shifts observed in commercial p-channel power VDMOSFETs during the NBT stressing are fitted using stretched exponential equation in order to estimate the device lifetime and discuss the impact of stress conditions and choice of extrapolation parameters. Excellent agreement found in later stress phases allowed for an accurate estimation of device lifetime for the lowest stress voltage applied, saving the time required for an extended experiment. More realistic lifetime estimates also are expected in the case of lower stress voltages, which additionally justify the need for using stretched exponential or some other suitable fit

Spontaneous recovery of positive gate bias stressed power VDMOSFETs

Spontaneous recovery of threshold voltage and channel carrier mobility in positive gate bias stressed power VDMOSFETs and the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed. Electron tunneling from neutral oxide traps associated with trivalent silicon /spl equiv/Si/sub o//sup ./ defects into the oxide conduction band is proposed as the main mechanism responsible for stress-induced buildup of positive oxide-trapped charge. Subsequent hole tunneling from the charged oxide traps /spl equiv/Si/sub o//sup +/ to interface-trap precursors /spl equiv/Si/sub s/-H is proposed as the dominant mechanism responsible for the interface trap buildup. A chain of mechanisms related to a presence of hydrogen species is proposed in order to explain changes of oxide-trapped charge and interface trap densities during the spontaneous recovery. Interface trap /spl equiv/Si/sub s//sup ./ passivation due to their reaction with hydrogen atoms is proposed as a main mechanism responsible for a decrease of interface trap density. Hydrogen molecule cracking at charged oxide traps /spl equiv/Si/sub o//sup +/, which leads to their neutralization, is proposed as the dominant mechanism responsible for a decrease of oxide-trapped charge density.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET*

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Effects of positive gate bias stress on radiation response in power VDMOSFETs

The effects of pre-irradiation positive gate bias stress on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift and mobility reduction in stressed devices have been observed, clearly demonstrating inapplicability of gate bias stressing for radiation hardening of power VDMOSFETs.