N. Stojadinovic

Analysis of CMOS transistor instabilities

Abstract A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.

Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs

The applicability of charge-pumping technique to characterize the oxide/silicon interface in standard power Vertical Double-diffused (VD)MOS transistors is studied. Qualitative analysis of the charge-pumping threshold and flat-band voltage distributions in the VDMOS structure, supported with rigorous transient numerical modeling of the charge-pumping effect, shows that the measurements can be carried out in the subthreshold region. This conclusion is confirmed by various experimental results. The characteristics, i.e. charge-pumping current versus gate top level, is studied in detail. The changes in the characteristics after /spl gamma/-ray irradiation are analyzed. A charge-pumping-based method for separate extraction of interface state density and density of charge trapped in the oxide after irradiation of VDMOSFETs is proposed. The validity and limitations of the method are studied by experiments and modeling.

Failure physics of integrated circuits — A review

Abstract This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems. In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed. In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes. In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.

The contribution of border traps to the threshold voltage shift in pMOS dosimetric transistors

The instability of pMOS dosimetric transistors in the form of threshold voltage drift could be an important source of errors in low dose measurements. The source of the drift is, according to the recent nomenclature, switching states concerned with near-interfacial oxide traps (border traps), and we have investigated them for 10 different types of specially prepared pMOS transistors. It has been found that the density of these states depends on the received dose, the bias during irradiation, the temperature, and the thickness of the gate oxide and its hydrogen content. A tunneling model that successfully describes the threshold voltage drift and explains these experimental results is presented. The possible physical picture of border traps and two specific structural models of defects in the SiO/sub 2/ which could be concerned with these experimental results are also discussed. >

Analysis of gamma-radiation induced instability mechanisms in CMOS transistors

Abstract Gamma-radiation induced instabilities of threshold voltage and gain factor of Al-gate and Si-gate CMOS transistors, as well as the underlying changes in positive gate oxide charge and interface trap densities are presented. The data are analyzed in terms of physico-chemical and electrophysical processes responsible for creation of the gate oxide charge and interface traps, and a generalized model which explains in detail the experimental data obtained is proposed.

Analysis of gamma-irradiation induced degradation mechanisms in power VDMOSFETS

Abstract In this paper, a detailed analysis of gamma-irradiation induced degradation of threshold voltage and gain factor in power VDMOSFETs, as well as the underlying changes in gate oxide charge and interface trap densities, is presented. Also, an analysis of the electrochemical mechanisms responsible for creation of the gate oxide charge and interface traps is performed, and a generalized model which explains in detail experimental results obtained is proposed. Finally, degradation of the threshold voltage and the underlying degradation mechanisms are analyzed in terms of the radiation tolerance of the power VDMOSFETs, with emphasis on the possibilities for its improvement.

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.

Instabilities in MOS transistors

Abstract An up-to-date review of results in the field of instabilities in MOS transistors is presented in this paper. First, the existing knowledge about the origin and features of gate oxide charge and interface traps, which are the major cause of instabilities in MOS transistors is systematized. After that, the latest findings concerning the influence of the gate oxide charge and interface traps on the threshold voltage and gain factor, as the main MOS transistor parameters, are given. Finally, an analysis of CMOS transistor instabilities is performed. This analysis points to the relationship between transistor characteristic instabilities and corresponding changes in the gate oxide charge and interface trap densities, and further, physico-chemical and electro-physical processes responsible.

The determination of zero temperature coefficient point in CMOS transistors

Abstract In this paper, the zero temperature coefficient (ZTC) point in CMOS transistors is considered. New analytical expressions for the optimal gate bias which ensures the drain current to be temperature independent are derived for both linear and saturation regions of MOS transistor operation. The expression for the linear region successfully accounts for the effect of dependence of the ZTC point on the drain bias. The new expression for the saturation region is somewhat more complex than the existing expression, but gives better agreement with experimental data.

Effects of electrical stressing in power VDMOSFETs

Abstract The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon Si o defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps Si o + to interface-trap precursors Sis–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects Si o Si o is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Sis–H with the charged oxide traps Si o + Si o and H+ ions are proposed to be responsible for interface trap buildup.