Angelo Kuti Lusala

A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications

In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while packet-switched sub-network is kept as simple as possible. In this way QoS is simply guaranteed without having to share resources, which often leads to a complex design. The proposed hybrid router architecture has been synthesized in FPGA and ASIC, and results show that a practical hybrid network-on-chip can then be built using the proposed approach.

Combining sdm-based circuit switching with packet switching in a NoC for real-time applications

In this paper we propose a hybrid network-on-chip “NoC”, which combines SDM-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The proposed NoC thus consists of two sub-networks. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while the packet-switched sub-network is kept as simple as possible. In this way QoS is easily guaranteed without having to share resources which often leads to a complex design. The SDM approach takes advantage of the wire abundance resulting from the increasing density of CMOS circuits. Synthesis results on a FPGA and ASIC show that a practical hybrid network-on-chip can then be built using the proposed approach.

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the proposed router architectures. 7 × 7 mesh NoCs were simulated in SystemC. Simulation results show that the probability of establishing paths through the NoC increases with the number of sub-channels and has its highest value when combining SDM with TDM, thereby significantly reducing contention in the NoC.

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range

We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs

With the increasing complexity and functionality of Real-Time embedded applications, Multiprocessor System-on-chip “MPSoC” offers the best tradeoffs in computation performances and power consumption. Designing MPSoC projects is time consuming and, often requires several competences and steps, spanning from hardware architecture to mapping application on the platform. This paper presents MPSoCDK, an integrated framework for rapid prototyping and validating MPSoC projects targeting FPGA devices. This platform, which includes several environments and toolchains, allows the designer to shorten the process of designing and exploring MPSoC projects, by simplifying the creation, the validation and the exploration of components in the MPSoC platform. Results show that the proposed framework can efficiently speedup the process of exploring, generating and programming multiprocessor platforms using a Graphical User Interface (GUI).

NoC Implementation in FPGA using Torus Topology

With the increasing capacity of FPGAs following the Moores law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a valid approach to meet communication requirements in SoC. Most of the current NoCs uses mesh topology. With mesh topology/, central channels are significantly solicited. This often leads to the congestion of the center area of the mesh. The solution for such situation is to add routers in the mesh or to use torus topology which, with the symmetry introduced on the routers in the opposite edges, has a good behavior to face congestion, and this, with a small increase of resources. In this paper, we propose a scalable implementation of a NoC for FPGA using torus topology. We proposed router architecture, a routing algorithm and a solution to the problem introduced by the long wires in torus topology.

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs

Adding vision capabilities to wireless sensors nodes (WSN) for the Internet-of-Things requires imagers working at ultra-low power (ULP) in nanometer CMOS systems-on-chip (SoCs). Such performance can be obtained with time-based digital pixel sensors (DPS) working at ultra-low voltage (ULV), at the expense of lower dynamic range, higher fixed-pattern noise (FPN) and thus poorer image quality. To address this problem, three key techniques were developed in this work for DPS pixels: wide-range adaptive body biasing, low-gating of the 2-transistor in-pixel comparator and digital readout performing delta-reset sampling with low switching activity and robust timing closure. These concepts were demonstrated by designing and fabricating a 128 × 128 CMOS image sensor array in a 65 nm low-power CMOS logic process. Operating at 0.5 V, it features an FPN of 0.66%, a dynamic range of 42 dB and a fill factor of 57% with a 4 μm pixel pitch, while consuming only 17 pJ/(frame.pixel) and 8.8 μW at 32 fps. These performances combined with the small silicon area of 0.69 mm2 makes the imager perfectly suitable for integration in ULP SoCs, targeting WSN applications.

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

This paper proposes a circuit-switched router which combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service “QoS” is easily guaranteed. The proposed router was synthesized on an FPGA and results show that a practicable network-on-chip “NoC” can be built with the proposed router architecture. Simulation results show an increase of the probability of establishing paths through the network.

A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications

This paper proposes a hybrid Network-on-Chip “NoC” which takes advantage of the best of packet switching and circuit-switching in order to handle efficiently both best-effort and streaming traffics generated by real-time applications. The proposed hybrid NoC consists of two sub-networks: a circuit-switched sub-network and a packet-switched sub-network. The circuit-switched sub-network combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the NoC and to improve resources usage, in this way, quality of service is easily provided for streaming traffic while the packet-switched sub-network handles the best-effort traffic. A 7*7 2D mesh NoC is built and simulated. Simulation results show that this approach allows an increase of the probability of establishing paths through the NoC, reducing thereby contention in the NoC with a reasonable hardware cost as shown in synthesis results.

A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks

We propose in this paper a hybrid router architecture which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffics generated in real-time applications. The SDM approach is used in circuit switching in order to increase path diversity, thus improving throughput while mitigating the low resource utilization inherent to circuit switching. In this way Quality of Service “QoS” is easily provided without sharing resources. The proposed hybrid router architecture has been synthesized on a FPGA and results show that increasing the number of sub-channels in a SDM-Channel does not considerably impact the area and the maximum clock frequency of the design. A 7x7 mesh NoC was simulated in SystemC. Simulation results show that the probability of path establishment increases with the number of sub-channels.