Guerric de Streel

Green SoCs for a sustainable Internet-of-Things

The vision of the Internet-of-Things (IoT) calls for the deployment of trillions of wireless sensor nodes (WSNs) in our environment. A sustainable deployment of such a large number of electronic systems needs to be addressed with a Design-for-the-Environment approach. This requires minimizing 1) the embodied energy and carbon footprint of the WSN production, 2) the ecotoxicity of the WSN e-waste, and 3) the Internet traffic associated to the generated data. In this paper, we study how ultra-low-power yet high-performance systems-on-a-chip (SoCs) in nanometer CMOS technologies can contribute to these objectives by allowing compact batteryless WSNs with on-node data processing. We then review latest results achieved at the Université catholique de Louvain in the field of green SoC design for a massive yet sustainable deployment of the IoT.

Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP.

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range

We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs

Adding vision capabilities to wireless sensors nodes (WSN) for the Internet-of-Things requires imagers working at ultra-low power (ULP) in nanometer CMOS systems-on-chip (SoCs). Such performance can be obtained with time-based digital pixel sensors (DPS) working at ultra-low voltage (ULV), at the expense of lower dynamic range, higher fixed-pattern noise (FPN) and thus poorer image quality. To address this problem, three key techniques were developed in this work for DPS pixels: wide-range adaptive body biasing, low-gating of the 2-transistor in-pixel comparator and digital readout performing delta-reset sampling with low switching activity and robust timing closure. These concepts were demonstrated by designing and fabricating a 128 × 128 CMOS image sensor array in a 65 nm low-power CMOS logic process. Operating at 0.5 V, it features an FPN of 0.66%, a dynamic range of 42 dB and a fill factor of 57% with a 4 μm pixel pitch, while consuming only 17 pJ/(frame.pixel) and 8.8 μW at 32 fps. These performances combined with the small silicon area of 0.69 mm2 makes the imager perfectly suitable for integration in ULP SoCs, targeting WSN applications.

Can we connect trillions of IoT sensors in a sustainable way? A technology/circuit perspective (Invited)

The Internet-of-Things is about to revolutionize our world with trillions of sensors to be deployed. However, this revolution raises sustainability issues at the economical, societal and environmental levels: security and privacy of the sensed data, environmental and economical costs of battery production and replacement, carbon footprint associated to the production of the sensor nodes, congestion of the RF spectrum due to numerous connected devices and electrical power consumption of the ICT infrastructure to support the Internet traffic due to the sensed data. In this paper, we show how these high-level challenges can be translated into IC design targets for three main functions of IoT nodes: digital signal processing (DSP), embedded power management (PM) and low-power wireless RF communications. We then demonstrate that CMOS technology scaling and ultra-low-voltage operation can help meeting these targets through an analysis of their benefits on simple yet representative DSP, PM and RF blocks.

A 65nm 1V to 0.5V linear regulator with ultra low quiescent current for mixed-signal ULV SoCs

A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.

Scaling perspectives of ULV microcontroller cores to 28nm UTBB FDSOI CMOS

Short-channel effects and variability in bulk technologies limit the interest of CMOS technology scaling for ultra-low-voltage (ULV) logic below 65nm because of the resulting penalty in the energy efficiency. FDSOI has already been predicted to be a good candidate to keep an excellent energy efficiency while increasing speed at ULV. In this paper, we confirm this result by synthesis results of microcontrollers at 0.35V. We show that the use of a mix of overdrive forward back biasing (FBB) voltages in 28nm FDSOI further improves the energy efficiency. Compare to bulk 65nm CMOS, we were able to reduce the energy per cycle by 64% or increase the frequency of operation by 7x while maintaining energy per operation below 3μW/MHz over a wide frequency range.

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape

We propose a UWB transmitter (TX) SoC designed for ultra-low voltage (ULV) in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management (PM), highly duty cycled digital baseband, programmable pulse shaping and wide-range on-chip adaptive forward back biasing (FBB) for VT reduction, PVT compensation and tuning of both the carrier frequency (CF) and the output power.

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools

The design of analog blocks is a bottleneck in a mixed-signal system designs due to the time-consuming layout step needing human intervention at each iteration of the optimization phase. In this paper, we propose a global automatic sizing and layout integrated methodology for analog block sizing including post-layout verification. The proposed optimizer is based on commercial digital place and route tools for the layout step and does not require custom layout procedures or dedicated layout-template framework. An analog cell library in LEF format with transistor, resistance and capacitance layout is used by the PnR tool allowing placement and routing of these elements. A post-layout netlist with parasitic resistances and capacitances as well as proximity effects is then extracted from generated the GDS file for post-layout simulation. A genetic algorithm is implemented as an optimization kernel allowing automatic sizing iteration. The optimizer is demonstrated in an advanced 28nm FDSOI process on typical analog blocks (two-stage basic amplifier, low-noise amplifier, ΔVT voltage reference and digital-controller oscillator).

Towards ultra-low-voltage wideband noise-cancelling LNAs in 28nm FDSOI

Software-defined and reconfigurable radio (SDR) architectures covering bands up to 6-GHz have recently drawn strong research attention for future wireless communications. These radios impose heavy Low Noise Amplifier (LNA) requirements over a wide frequency range. In order to be integrated in complex Systems-on-a-Chip (SoCs), such LNAs should also be implemented in advanced CMOS technologies to follow SoC development trends while benefiting from the high fT and fmax available with technology scaling. In this work, we study the potential of 28nm FDSOI for operating inductorless wideband LNAs at Ultra-Low-Voltage (ULV) through a sizing framework combining extensive design space exploration and small signal modelling.