Angelo Nagari

Low-voltage double-sampled /spl Sigma//spl Delta/ converters

In theory, double-sampling in second-order /spl Sigma//spl Delta/ analog-to-digital converters (ADC) can enhance the signal-to-noise ratio (SNR) by 15 dB. In practice however, the SNR performance is usually severely degraded because of mismatches occurring in switched-capacitors (SC). This paper introduces a simple method to solve this problem. Regarding /spl Sigma//spl Delta/ digital-to-analog converters (DAC), in addition to double-sampling, the accompanying use of internal decimation helps to relax the bandwidth requirements of the opamps. Both circuitries are to be operational to supply voltages as low as 1.5 V by using clock bootstrapping. Chip implementation is in double-poly, 2-metal technology featuring 0.5 /spl mu/m minimum channel lengths.

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effec- tive sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping cir- cuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5- m CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm dissipating 550 W while the digital-to-analog converter occupies 0.28 mm dissipating 600 W.

A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter

A fundamental block in telecommunication systems is the high-selectivity bandpass filter centered at the intermediate frequency (IF). In this paper, a BiCMOS high-Q (Q=29) 10.7-MHz switched-capacitor (SC) bandpass filter to be used in the FM receiver channel has been developed. The filter uses low-gain large-bandwidth opamps. The opamp finite gain effects have been compensated using an SC integrator suited for high-Q filters. The particular SC finite-gain compensation scheme allows the implementation of double sampling to relax opamp bandwidth requirements. To reduce total output noise, noisy T-cell networks (often used in other cases) have been avoided. The resulting large capacitors (the largest capacitor is 8.5 pF) are driven by a Class AB output buffer. In a 1.2-/spl mu/m BiCMOS technology, the filter prototype has an area of about 1.6 mm/sup 2/ and a power consumption of 17 mW. The in-band noise density is 380 nV//spl radic/Hz, and the dynamic range is about 68 dB for a 3% IM.

A -80 dB THD, 4 V/sub pp/ switched capacitor filter for 1.5 V battery-operated systems

A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V/sub pp/ output voltage is presented. A measured p-weighted noise of 120 /spl mu/V/sub rms/ leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm/sup 2/ in a 0.8 /spl mu/m CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply.

A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear /spl Sigma//spl Delta/ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm/sup 2/ in a 0.5-/spl mu/m n-well double-poly triple-metal CMOS process.This paper describes a receive baseband ADC for a GSM cellular radio system. The circuit consists of two second-order double-sampled semi-bilinear /spl Sigma//spl Delta/ modulators followed by two 576-tap digital FIR GSM-channel filters with offset calibration. The complete A/D achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7 V supply. The area is 1.6 mm/sup 2/ in a 0.5 /spl mu/m N-well double-poly, triple-metal CMOS process.

A 0.01%THD, 70dB PSRR Single Ended Class D using variable hysteresis control for headphone amplifiers

Switching audio amplifiers are widely used in HBridge topology thanks to their high efficiency; however low audio performances in single ended power stage topology is a strong weakness leading to not be used for headset applications. This paper explains the importance of efficient error correction in Single Ended Class-D audio amplifier. A hysteresis control for Class-D amplifier with a variable window is also presented. The analyses are verified by simulations and measurements. The proposed solution was fabricated in 0.13µm CMOS technology with an active area of 0.2mm2. It could be used in single ended output configuration fully compatible with common headset connectors. The proposed Class-D amplifier achieves a harmonic distortion of 0.01% and a power supply rejection of 70dB with a quite low static current consumption.

A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

A low-voltage, low-power, CMOS-programmable analog front-end IC for 2.7-V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 14-bit uniform codec. The main objective of the uniform codec is to achieve a signal-to-noise (S/N) and a signal-to-total-harmonic-distortion (S/THD) ratio for the complete A/D and D/A paths better than 80 dB at full scale. A high-performance speech interface is made of a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, and two power amplifiers capable of driving toads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/ output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purposes, and a dedicated pulsewidth-modulated (PWM) output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four-wire control interface. This performance has been achieved from a 2.7-V supply with operative and standby power consumptions of 13 mW and 1.5 /spl mu/W, respectively. The chip area is 10.5 mm/sup 2/ (including scribe line) in a 0.5-/spl mu/m n-well CMOS technology.

A 3 V 10 MHz pseudo-differential SC bandpass filter using a gain-enhancement replica amplifier

Double-sampling has proven to be suitable for the design of SC filters. Filters are implemented with a simple pseudo-differential common-source amplifier structure. A pseudo-differential approach does not require common-mode feedback loading the opamp differential output, or a tail current source that can limit the positive or negative output swing. This allows reaching the theoretical maximum bandwidth and swing of the opamp. Finally, filters can be realized with a replica amplifier (RA) structure that preserves both the swing and the speed of the main amplifier (MA). A schematic of the complete pseudo-differential opamp circuit is given.

A topological comparison of PWM and hysteresis controls in switching audio amplifiers

The switching audio amplifiers are widely used in various portable and consumer electronics because of their high efficiency, but suffer from low audio performances due to inherent nonlinearity. This problem can be limited with efficient feedback from the output power stage. The research community focuses now to the efficient error correction by feedback control systems. This paper proposes a theoretical and practical comparison between the PWM control and our proposed hysteresis solution. These topologies are widely used in a very wide range of applications. This work shows that the hysteresis solution offers both lower power consumption and higher audio performances for embedded audio application.

An review of fully digital audio class D amplifiers topologies

Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. This paper presents topologies of full digital class D amplifiers in order to remove the analog DAC in the amplification path. This approach increases the playback time of embedded system. In first session, open-loop digital class D and digital modulation are discussed. The characterization of an open-loop class D prototype, using a CMOS 130 nm ASIC and a FPGA, confirms the advantage of such systems to reach a long battery life. Then, solutions with closed-loop topologies are proposed to increase linearity and power supply rejection of digital class D. Simulation results of closed-loop topologies, showing an increased in sound quality, are presented as well.