Carlo Dallavalle

Low-voltage double-sampled /spl Sigma//spl Delta/ converters

In theory, double-sampling in second-order /spl Sigma//spl Delta/ analog-to-digital converters (ADC) can enhance the signal-to-noise ratio (SNR) by 15 dB. In practice however, the SNR performance is usually severely degraded because of mismatches occurring in switched-capacitors (SC). This paper introduces a simple method to solve this problem. Regarding /spl Sigma//spl Delta/ digital-to-analog converters (DAC), in addition to double-sampling, the accompanying use of internal decimation helps to relax the bandwidth requirements of the opamps. Both circuitries are to be operational to supply voltages as low as 1.5 V by using clock bootstrapping. Chip implementation is in double-poly, 2-metal technology featuring 0.5 /spl mu/m minimum channel lengths.

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effec- tive sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping cir- cuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5- m CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm dissipating 550 W while the digital-to-analog converter occupies 0.28 mm dissipating 600 W.

PCM telephony: reduced architecture for a D/A converter and filter combination

Large dynamic range and high power-supply rejection ratio (PSRR) are achieved in a pulse-code-modulation (PCM) decoder by using differential circuit techniques and by reducing the number of operational amplifiers on the interpolation filter to four (including the output buffer). This reduction is achieved by: (1) exploiting the sin x/x distortion and using a simple integrating configuration in the digital-to-analog converter; and (2) properly manipulating the signal flowgraph of the filter. >

A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

A low-voltage, low-power, CMOS-programmable analog front-end IC for 2.7-V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 14-bit uniform codec. The main objective of the uniform codec is to achieve a signal-to-noise (S/N) and a signal-to-total-harmonic-distortion (S/THD) ratio for the complete A/D and D/A paths better than 80 dB at full scale. A high-performance speech interface is made of a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, and two power amplifiers capable of driving toads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/ output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purposes, and a dedicated pulsewidth-modulated (PWM) output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four-wire control interface. This performance has been achieved from a 2.7-V supply with operative and standby power consumptions of 13 mW and 1.5 /spl mu/W, respectively. The chip area is 10.5 mm/sup 2/ (including scribe line) in a 0.5-/spl mu/m n-well CMOS technology.

A 5-V CMOS programmable acoustic front-end for ISDN terminals and digital telephone sets

A 5-V CMOS programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions, fulfilling all D3/D4 and CCITT specs. Moreover, it implements the main analog interfaces required for the speech channel (low-noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a four wire separated control interface or by means of a serial control channel multiplexed with the PCM voice/data channel in a GCI compatible format. Chip area is 30 mm/sup 2/ in a 1.5-/spl mu/m CMOS technology. The active/stand-by power consumption is 60 mW/0.2 mW from a single 5-V supply. All circuits are designed to meet performance objectives over a voltage range from 4.5 V to 5.5 V and a temperature range from -40/spl deg/C up to 85/spl deg/C. >

A 5V CMOS Programmable Acoustic Front-End for ISDN Terminals and Digital Telephone Sets

A 5V programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions fulfilling and exceeding all D3/D4 and CCITT specs. It implements the analog interfaces required for the speech (low noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a separate four wire control interface or by means of a serial control channel multiplexed with the PCM voice/data in a GCI compatible format. Chip area is 30 mm2 in a 1.5¿ CMOS technology. Active/stand-by power consumption is 60mW/0.2mW from a single 5V supply.

A high-performance analog front-end 13-bits linear codec for 3V digital cellular phones

A low-voltage, low-power, CMOS programmable Analog Front-End IC for 3 V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 13-bits linear codec. Its high performance speech interface results in a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, while it is capable of driving loads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/, output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purpose, and a dedicated pulse-width modulated output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four wire control interface. These performances have been achieved from a 3 V supply with operative and stand-by power consumptions of 21 mW and 1.5 /spl mu/W, respectively. Chip area is 22.7 mm/sup 2/ in a 0.8 /spl mu/ CMOS process.

A 2.7 V CMOS single chip baseband processor for CT2/CT2+ cordless telephones

A low voltage, low power CMOS single chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 AD-PCM coder/decoder, a Burst Mode Logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. It can be easily interfaced with standard microcontrollers through a parallel interface. It can operate from a 2.7 V minimum supply with operative and stand-by power consumptions of 35 mW and 25 /spl mu/W, respectively. Maximum operative supply is 5.5 V. Chip area is 55.5 mm/sup 2/ in a 0.8 /spl mu/ N-well CMOS process.

Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing

In the deep submicron era, leakage power has become a first rank component, not only in the battery powered devices but in high performance broadband and networking processors. SoC complexity implies hundred millions transistors then large die size which combined with 30cm diameter wafers lead to large process variations, therefore to highly spread leakage power. A method aimed to reduce this leakage power variation through the combined use of dedicated cell libraries, monitor structures and programmable charge pump reverse bias substrate generators is proposed.

A 2.7-V CMOS single-chip baseband processor for CT2/CT2+ cordless telephones

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 /spl mu/W, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70/spl deg/C. Chip area (including scribe line) is 55.5 mm/sup 2/ in a 0.8 /spl mu/m N-well double-metal single-poly CMOS process with implanted capacitors.