Raoul Tawel

Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips

Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits.

Evolution of analog circuits on field programmable transistor arrays

Evolvable Hardware (EHW) refers to HW design and self reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. In addition, we illustrate with an example how evolution can recover functionality lost due to an increase in temperature. In the particular case of space applications, these characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life.

Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits

The paper describes the architectural details of a fine-grained programmable transistor array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. A PTA chip was built in CMOS to allow circuits obtained through evolutionary design using a simulated PTA to be immediately deployed and validated in hardware and, moreover, enables a benchmarking and comparison of evolutions carried out via simulations only (extrinsic evolution) with the chip-in-the-loop (intrinsic) evolutions. The evolution of an analog computational circuit and a logical inverter are presented. Synthesis by software evolution found several potential solutions satisfying the a priori constraints, however, only a fraction of these proved valid when ported to the hardware. The circuits evolved directly in hardware proved stable when ported to different chips. In either case, both software and hardware experiments indicate that evolution can be accelerated when gray-scale (as opposed to binary switches) were used to define circuit connectivity. Overall, only evolution directly in hardware appears to guarantee a valid solution.

A radial basis function neurocomputer implemented with analog VLSI circuits

An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.<<ETX>>

Analog VLSI neural networks: implementation issues and examples in optimization and supervised learning

Time-critical neural network applications that require fully parallel hardware implementations for maximal throughput are considered. The rich array of technologies that are being pursued is surveyed, and the analog CMOS VLSI medium approach is focused on. This medium is messy in that limited dynamic range, offset voltages, and noise sources all reduce precision. The authors examine how neural networks can be directly implemented in analog VLSI, giving examples of approaches that have been pursued to date. Two important application areas are highlighted: optimization, because neural hardware may offer a speed advantage of orders of magnitude over other methods; and supervised learning, because of the widespread use and generality of gradient-descent learning algorithms as applied to feedforward networks. >

Custom VLSI ASIC for automotive applications with recurrent networks

Demands on the performance of vehicle control and diagnostic systems are steadily increasing as a consequence of stiff global competition and government mandates. Neural networks provide a means of creating control and diagnostic strategies that will help in meeting these demands efficiently and robustly. This paper describes a VLSI design that permits such networks to be executed in real time as well as the application in misfire detection, that served as a focus for the collaborative effort.

Learning in analog neural network hardware

Abstract Hardware implementations of neuroprocessor architectures are currently enjoying commercial availability for the first time ever. This development has been caused in part by the requirement for real-time solutions to time critical neural network applications. Massively parallel asynchronous neuromorphic representations are inherently capable of very high computational speeds when properly cast in the “right stuff”, i.e. electronic or optoelectronic hardware. However, hardware based learning in such systems is still at a primitive stage. In practise, simulations are typically performed in software, and the resulting synaptic weight capturing the input-output transformation subsequently quantized and down-loaded onto the neural hardware. However, because of the numerous discrepancies between the software and hardware, such systems are inherently poor in performance. In this paper we report on chip-in-the-loop learning systems assembled from custom analog “building blocks” hardware.

Different approaches to implementing a radial basis function neurocomputer

Describes and analyses three different approaches to implementing a radial basis function neural network with an electronic neurocomputer. This type of network utilizes a radial basis function as the transfer function of the neuron. The three different approaches are: (1) a completely analog system using custom analog VLSI circuits, (2) a completely digital system using a commercially available digital signal processor, and (3) a hybrid analog/digital system using both analog VLSI circuits and a digital signal processor. The circuits required for all three of these approaches have been designed, fabricated, and tested. Two of these approaches, the completely digital system and the hybrid system, have been realized in hardware. Circuit performance is analysed, and the resulting system implications are considered. The tradeoffs of the three different approaches are presented, and a method is proposed for determining an optimal system in light of the constraints imposed by the application.<<ETX>>

A neural architecture for the assignment problem: simulation and VLSI implementation

A competitive neural network architecture and hardware implementation is described. It is capable of solving first-order assignment problems. Each member of one set may be independently matched or blocked to a range of members of another set. One processing unit (PU) is used for each possible pairing of members, and analog association costs are applied directly to PU inputs as thresholds. Blocking constraints are enforced by circuits that oversee PU activations in each row and column, and modulate their excitations as required. Mean-field annealing is used to avoid local minima. Simulation results for problems to 64*64, with random costs, suggest that the hardware can be expected to settle in at most a few milliseconds. Since the simulation settled to the optimal solution in almost all cases it is apparent that the hardware can be expected to find at least good solutions. Characterization of an analog VLSI test chip implementing the PU and row/column constraint circuits is presented.<<ETX>>

A CMOS UV-programmable non-volatile synaptic array

A CMOS floating-gate-based nonvolatile analog circuit that implements an array of simple processing synaptic elements is described. In this implementation, unfocussed ultraviolet (UV) radiation is utilised to photo-activate electrons in the silicon conduction band across an oxide barrier onto another slab of silicon that forms an isolated gate of a transistor. It is based on a four-quadrant analog multiplier circuit requiring both X and Y differential inputs, where one such Y-input node is UV programmable. This method relies on exposing the synaptic array with UV light and serially writing the connection weights. These non volatile multiplier cells have been implemented as a fully connected 32*32 cross-bar synaptic matrix using standard p-well CMOS VLSI fabrication process with a 2- mu m feature size.<<ETX>>