Anis Boudabous

Architecture and FPGA implementation of the CORDIC algorithm for fingerprints recognition systems

In this paper, we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow.

Reconfigurable architecture of VDF filter for multidimensional data

In this paper, we present a hardware reconfigurable architecture of vector directional filter (VDF) and an experimental validation based on HW/SW implementation context. An FPGA with a Nios II processor combines the benefits of a programmable logic component as well as a microprocessor. VDF is very useful in multidimensional data (such as color images) for noise removal and details preservation. Comparative results between simulations of ANSI-C and hardware implementation are given. An estimate method of nonlinear function is presented and serves as an approximation for the appropriate hardware implementation on FPGA. Finally, to verify the functionality of the implementation, a validation state using FPGA platform has been performed. This validation demonstrated that our implementation hardware system speeds up the filtering process as well as preserving a high data quality (image quality). Copyright

FPGA Codesign Implementation of Vector Directional Filter

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.

FPGA implementation of vector directional distance filter

In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII development board, we demonstrate a clearly improvement in the filtering speed compared to the software solution. Experiments on a large and diverse image sets show that our implementation approach achieves an excellent balance between simplicity, accuracy, and computational speed.

Reduction of impulsive noise in colour image using an Adaptive Vector Distance Directional Filter

In this paper, multichannel image processing using an adaptive approach is the subject of our study. Thus, we have proposed a new Adaptive Vector Directional Distance Filter (VDDF). Simulation results illustrate that this new proposed filter outperforms the classic Vector Directional Distance Filter when images are contaminated with impulsive noise. In addition, efficiency of this filter is proven since it provides an excellent balance between the noise attenuation and the signal-details preservation.

Complexity study of the Gamma correction method for text extraction from complex images

In this paper, we present a complexity study of the Gamma correction method for automatic text extraction from complex images. This study is based on the build of a simple and adequate algorithm for future hardware solution. Then, a profiling study for each function of the proposed solution was done. After validation, using C/C++ environment, a comparison with the OpenCV based algorithm developed by ESIEE Paris was performed. We show a clear improvement in the run time. Profiling and experimental results, using diverse images prove that our study achieves an excellent balance between simplicity, precision, and computational speed. This study will be operated in the future work of hardware implementation.

FPGA Implementation of the CORDIC Algorithm for Fingerprints Recognition Systems

In this paper, we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow.

Hardware implementation and experiment validation of the VDDRHF color image filter

This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

HW/SW FPGA implementation of Vector Median Filter

In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.