Ankur Srivastava

Security and Vulnerability Implications of 3D ICs

Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D integration technology emerges as a viable option to improve chip performance and increase device density in a direction orthogonal to costly device scaling. As 3D integration is becoming a promising technology for next-generation chip design, recent years have seen a huge proliferation of research literature exploiting it from a security perspective. This paper presents a survey on the current state of 3D integration technology from a security perspective and summarizes its security opportunities and challenges. We report current research work on 3D integration based security in three major applications: supply chain attack prevention, side-channel attack mitigation, and trustworthy computing system design. The security advantages and opportunities of 3D integration in these security applications are highlighted. Besides, the paper discusses new vulnerabilities risen by 3D integration that require researchers attention. Based on the survey result, we summarize the distinct characteristics of 3D ICs and investigate their impacts on security-aware 3D IC designs.

Online TSV health monitoring and built-in self-repair to overcome aging

TSV redundancy and reconfiguration in 3D-ICs is a well-known method for overcoming TSV manufacturing faults. However, additional post-manufacturing faults can manifest over the lifetime of the chip due to aging effects such as electromigration and thermal cycling. This paper presents a scheme which leverages the existing reconfiguration infrastructure and unused redundant TSVs to overcome runtime faults caused by aging. Failures due to aging faults are predicted by tracking the degree of degradation on each TSV over time, allowing reconfiguration to occur before failure actually occurs. The experimental results reported in this paper indicate that the proposed tracking scheme presented in this work can lead to a 13.8% increase in MTTF of the simulated circuit, while maintaining a sampling rate of less than one sample per week.

A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs☆

Abstract In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.

Electromigration-aware placement for 3D-ICs

This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSVs EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSVs EM is mutually influenced by neighboring TSVs (due to TSV EMs dependence on TSV-induced thermal mechanical stress) and strongly affected by temperature, iterative optimizations are performed to obtain the optimal TSVs distribution and a desired TSVs temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with a conventional wirelength centered 3D placer, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.

Continued frequency scaling in 3D ICs through micro-fluidic cooling

Core scaling has largely replaced frequency scaling in general purpose microprocessors in the last decade. This is largely because of the high temperature and power dissipation associated with frequency scaling in traditional air cooled systems. In this paper we investigate how this trend changes when micro-fluidic cooling is added to a chip. Compared to traditional air cooling, micro-fluidic cooling can remove significantly more heat from the system, preventing thermal violations and reducing leakage power. This not only makes frequency scaling thermally feasible, but also increases the energy efficiency of higher frequency processors. Vertical integration of circuits (3D ICs) is a promising technology for facilitating a large number of cores, due to the limits on chip footprint size imposed by manufacturing yields. In this work we investigate the advantages of adding micro-fluidic water cooling to 3D stacked DRAM processors and show that such an approach can improve performance an average of 57.4% by making higher frequencies and more cores thermally feasible and improve energy efficiency 13.4% by reducing leakage power.

Unlocking the true potential of 3D CPUs with micro-fluidic cooling

As technology scaling is coming to an end, 3D integration is a promising technology to continue transistor density scaling in the future and facilitate new architectural designs. However heat removal is a serious challenge in 3D ICs. A promising solution is micro-fluidic (MF) cooling. In this paper we argue that aggressive cooling methods are necessary to unlock the true potential of 3D ICs. We simulate a spectrum of 3D CPU architectures which offer vast improvements to performance, but are inefficient and thermally infeasible with air cooling alone. Our results show that integrating micro-fluidic cooling can increase average performance by 2.62x and energy efficiency by 1.78x by unlocking new architectural configurations.

Co-optimization of TSV assignment and micro-channel placement for 3D-ICs

The three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating the use of active cooling schemes such as micro-channel liquid coolings. Both TSVs and micro-channels go through the interlayer regions of 3D-IC resulting in potential resource conflict. This paper investigates the co-optimization of TSV assignment to interlayer nets and micro-channel allocation such that both wirelength and micro-channel cooling energy are co-optimized. We propose a multi-commodity flow based formulation to solve the co-optimization. The experimental results show that, our approach achieves 51% cooling power savings or 6.08% wire length reduction compared with the approaches that assign TSVs and allocate micro-channels separately.

Co-Placement for Pin-Fin Based Micro-Fluidically Cooled 3D ICs

3D ICs with through-silicon vias (TSVs) can achieve high performance while exacerbating the problem of heat removal. This necessitates the use of more aggressive cooling solutions such as micropin-fin based fluidic cooling. However, micropin-fin cooling comes with overheads such as non-uniform cooling capacity along the flow direction and restriction on the position of TSVs to where pins exist. 3D gate and TSV placement approaches un-aware of these drawbacks may lead to detrimental effects and even infeasible chip design. In this paper, we present a hierarchical partitioning based algorithm for co-placing gates and TSVs to co-optimize the wire-length and in-layer temperature uniformity, given the logical level netlist and layer assignment of gates. Compared to the wire-length driven gate placement followed by a TSV legalization stage, our approach can achieve up to 75% and 25% reduction of in-layer temperature variation and peak temperature, respectively, with the cost of 13% increase in wire-length.Copyright

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling

In this work we consider new 3D IC processor architectures that become feasible only when aggressive cooling is used. In traditional air cooled 3D processors, heat removal is a big issue, and so designers often pursue low performance architectures in order to prevent thermal violations. We attempt to explore the new design space that is available to computer architects when micro-fluidic cooling is applied to the 3D chip. We show that adding more memory controllers to a 3D processor can offer the potential for huge increases in performance, but also drastically increases the temperature of an uncooled chip, making them infeasible. With micro-fluidic cooling, these performance increases become realizable and new high performance architectures can be designed when cooling is co-designed with the architecture. We observe a 2.4x increase in average performance when comparing a 3D stacked memory processor with and without micro-fluidic cooling. This performance increase occurs because the cooling unlocks the possibility of adding more memory controllers as well as more aggressive frequency scaling. Cooling also improves the energy efficiency of the processors since a slight increase in cooling power helps to significantly reduce the leakage levels. This combined with improvements in performance due to aggressive cooling helps to increase energy efficiency on average 16.8x.

Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

In 3D ICs, interlayer communication is achieved using through-silicon-vias (TSVs), which can suffer from cross coupling if placed naïvely. In this paper, cross coupling between TSVs is modeled, and a chip-scale TSV coupling mitigation scheme is presented using TSV shielding. A geometric coupling model is developed which is simple enough to quickly estimate the pairwise coupling between TSVs, unlike circuit models of coupling that have been proposed in previous works. Our geometric models ability to make fast accurate estimations of chip-scale cross coupling make it a good model to use for shield placement optimization.n A shield placement algorithm is presented which reduces TSV coupling by formulating a min cost flow (MCF) problem based on the proposed model. Our algorithm is compared to another shield placement algorithm presented in [9] which is based on a circuit model of coupling. Experimental results show that the algorithm proposed here is able to reduce the total cross coupling in a layout an average of 4.59x more than the other algorithm while using the same number of shields. Alternatively, our algorithm uses an average of 88% less shields to shield a layout to the same degree as the shielding schemes produced by the other algorithm.