Annalisa Cappellani

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Comparison of Junctionless and Conventional Trigate Transistors With

Junctionless accumulation-mode (JAM) devices with channel lengths Lg down to 26 nm were fabricated on a trigate process and compared to conventional inversion-mode (IM) devices. This letter represents the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) . The JAM devices show better channel mobility (when moderately doped) and lower gate capacitance than the IM control counterparts at matched Ioff. However, the JAM devices also show reduced gate control and degraded short-channel characteristics. The observed degraded behavior of JAM relative to IM is explained with the aid of device simulations and a simple analytic model of the channel charge.

L_{g}

For the past 40 years, relentless focus on Moores Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, the paper reviews device options beyond the ultimate CMOS device.