Matthew Hillsboro Metz

High-/spl kappa//metal-gate stack and its MOSFET characteristics

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (ID) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase ID by more than 20X.

Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO<inf>x</inf>-2nm InP) in the In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t<inf>OXE</inf>) and low gate leakage (J<inf>G</inf>) and (ii) effective carrier confinement and high effective carrier velocity (V<inf>eff</inf>) in the QW channel. The L<inf>G</inf>=75nm In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V<inf>DS</inf>=0.5V.

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (LSIDE) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5Å with low JG, and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar TOXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

III–V field effect transistors for future ultra-low power applications

This paper summarizes the electrostatics and performance of III-V field effect transistors including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs (TFETs). The electrostatics of the III-V devices is shown to improve from thick body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET structures, sub-threshold slope (SS) steeper than 60 mV/decade has been demonstrated in III-V TFETs. These III-V devices, especially the 3-D tri-gate MOSFET and TFET, are viable options for future ultra low power applications.

MOVPE III–V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications

This research work demonstrates, for the first time, that the material quality of MOVPE III–V QWFET structures on Si can be matched to that of the best MBE III–V QWFET structures on Si. The MOVPE grown In<inf>0.53</inf>Ga<inf>0.47</inf>As QW layer on Si exhibits high Hall mobility of ∼8000cm²/V-s at 300K, matching that obtained by MBE growth on lattice matched InP (the “gold standard”).

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC substrate

GaN is a promising material for LED lighting [1], high voltage power electronics [2] and high power RF applications [3]. GaN HEMT and MOS-HEMT with AlGaN [4] or AlInN [5] polarization layer have been widely studied. In this work we investigate the effects of Al_0.83In_0.17N polarization layer thickness scaling on the device characteristics of Al_0.83In_0.17N/AlN/GaN MOS-HEMTs on SiC substrates. We have experimentally observed “negative” capacitance and subthreshold swing (SS) steeper than 40 mV/dec in GaN MOS-HEMTs with thin Al_0.83In_0.17N polarization layer, where composition modulation of Al% and In% is observed.