Anne McGuire

Airborne chemical contamination of a chemically amplified resist

We have found that the performance of the t-BOC/onium salt resist system is severely degraded by vapor from organic bases. This effect is very pronounced and can be observed when the coated wafers stand for 15 minutes in air containing as little as 15 parts per billion (ppb) of an organic base. The observed effect, caused by this chemical contamination, depends on the tone of the resist system. For negative tone systems the UV exposure dose, required to obtain the correct linewidth, increases. While for the positive tone system, one observes the generation of a skin at the resist-air interface. Both effects are caused by the photogenerated acid being neutralized by the airborne organic base. There are a wide variety of commonly used materials which can liberate trace amounts of volatile amines and degrade resist performance. For example, fresh paint on a laboratory wall can exhibit this detrimental effect. These effects can be minimized by storing and processing the resist coated wafers in air that has passed through a specially designed, high efficiency carbon filter. The implementation of localized air filtration, to bathe the resist in chemically pure air, enabled this resist system to operate in a manufacturing environment at a rate of 100 wafers/hour.

Optimizing style options for subresolution assist features

Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBMs early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

Controlling the sidewall angle of advanced attenuated phase-shift photomasks for 14nm and 10nm lithography

As optical lithography is extended to the 14nm and 10nm technology nodes, sidewall angle (SWA) control of photomask features becomes increasingly important. The experiments to be reported here study SWA for advanced attenuated phase-shift photomasks. SWA is evaluated from three perspectives. First, the effects of mask etch process parameters will be studied. Second, the effects of local mask environment, such as etch loading and line width, will be tested. Finally, a variety of SWA measurement methods will be compared.

EUV mask line edge roughness

Extreme ultraviolet (EUV) mask fabrication faces many unique challenges, including more stringent line edge roughness (LER) requirements. EUV mask absorber LER will need to be reduced to reliably meet the 2013 International Roadmap for Semiconductors line width roughness target of 3.3 nm. This paper will focus on evaluating resists modified and deployed specifically to reduce LER on EUV masks. Masks will be built, and the final mask absorber LER reported considering multiple imaging and analysis techniques. An assessment of best methods for mask LER analysis will be provided and used to judge resist performance.

Study and comparison of negative tone resists for fabrication of bright field masks for 14nm node

In order to meet the challenging patterning requirements of the 14 nm node, the semiconductor industry has implemented use of negative tone develop (NTD) and other tone inversion techniques on wafer to enable use of bright field masks which provide an improved lithography process window.1,2,3 Due to e-beam write time and mask pattern fidelity requirements, the increased use of bright field masks means that mask makers must focus on improving the performance of their negative tone chemically amplified resist (NCAR) processes. In addition, the move to heavy use of bright field masks is introducing new challenges for mask makers. Bright field masks for 14 nm critical layers are required to have opaque sub-resolution assist features (SRAFs) as small as 50 nm while at the same time having across mask critical dimension uniformity (CDU) of less than 2 nm (3 sigma) to meet the 2014 ITRS targets.4 Achieving these specifications is particularly difficult for bright field contact and via level masks. This paper will survey the performance requirements for NCAR resists for building 14 nm critical level masks. As part of this survey, the results of current commercially available and development NCAR resists will be compared. The study will focus on key elements of the resist process pertaining to line edge roughness, pattern fidelity, minimum feature size, and critical dimension control through density with differences in resist type, sensitivity, and thickness. In addition, use of a novel flow cell test apparatus for detailed study of the develop loading performance of the NCAR resists will be described. Data showing the current capability of these NCAR materials as well as remaining 14 nm node performance gaps and issues will be presented.

Revisiting mask contact hole measurements

Contact holes represent one of the biggest critical dimension (CD) mask metrology challenges for 45nm technology mask development. The challenge is a consequence of both wafer and mask sensitivities. Large mask error factors and the small process windows found when contact holes are imaged on wafers impose very tight mask specifications for CD uniformity. The resultant CD error budget leaves little room for mask metrology. Current advanced mask metrology deploys a CD-SEM to characterize the mask contact hole CD uniformity. Measuring a contact hole is complex since it is inherently two-dimensional and is not always well-characterized by one-dimensional x- and y-axis measurements. This paper will investigate contact metrics such as line edge roughness (LER), region of interest (ROI) size, area, and CD sampling methods. The relative merits of each will be explored. Ultimately, an understanding of the connection between what is physically measured on the mask and what impacts wafer imaging must be understood. Simulations will be presented to explore the printability of a contact holes physical attributes. The results will be summarized into a discussion of optimal contact hole metrology for 45nm technology node masks.

Pushing SRAM densities beyond 0.13-μm technology in the year 2000

For any given technology in the logic foundry business it is highly desirable to offer a dense SRAM design which can be manufactured using the same mask and wafer toolsets as the base design. This paper discusses the lithographic issues related to imaging a pseudo-0.11 um technology within a 0.13 um ground rule, including optical proximity correction, design, mask making issues, and comparison of top-down SEM to simulation. To achieve a dense SRAM and quick turn around on design shrinks, simulation and experimental feedback are key. In this study, SRAM cells were redesigned, and a well calibrated resist and etch bias model, in conjunction with a fast micro lithographic aerial image simulator and mask model, were used to predict and optimize the printed shapes through all critical levels. One of the key issues is the ability to correlate and feedback experimental data into the resist simulation. Experimental results using attenuated phase shift masks and state-of-the-art resist process technology are compared to the simulation.

Image shortening and process development in BEOL lithography

The problem of image shortening is well known in semiconductor lithography. As rectangular features decrease in width, the length of the feature will print smaller than the mask image length. This problem places a constraint upon overall device design because space must be allowed for line extensions and/or adding to the side of features. Making corrections for image shortening requires mask redesign, which increases the time and cost of new product development.

Advanced lithography kits: serifs and hammerhead

Resolution enhancement techniques and higher NA exposure are employed to meet the lithography requirements imposed by aggressive shrinks to chip feature sizes. For certain critical levels, like storage and isolation patterning of DRAM devices, the capability to exactly reproduce the mask layout is limited. Severe corner rounding and line image shortening can occur. Such phenomena can be significant contributors to side effects like current leakage, inadequate retention time, stress, and perhaps yield loss. Our development work has shown that the use of Serif and Hammerhead structures can improve resolution printing. Moreover, better process latitude and CD control can be achieved. This paper gives an overview of these innovative techniques. It includes the consideration of different design layouts based on simulations, as well as mask making limitations e.g. mask inspection capability. The benefits of these techniques are discussed and illustrated with detailed lithographic performance data and SEM pictures.