Timothy A. Brunner

EUV vote-taking lithography: crazy... or not?

Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980’s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1/N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N-1 masks. Vote-taking has recently been brought under the attention again for consideration in EUV lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations. This paper provides a thorough experimental assessment of the implementation of vote-taking, and discusses its pro’s and con’s. Based on N=4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. Additionally, we found that blending different mask images brings clear benefit to the imaging, and provide experimental confirmation of improved local CDU and intra-field CDU, reduction of stochastic failures, improved overlay, ... Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner. This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. While defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.

EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV? (Conference Presentation)

The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term “EPE” has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of “Good Fields”1 and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma “value” design-rules need to be tested to ensure high yield. The “value” can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement error distributions and appropriate design-rule setting. While CD distributions with long tails coming from stochastic effects do bring increased risk of failure (especially on chips that may have over a billion failure opportunities per layer) there are other sources of variation that have sharp cutoffs, i.e. have no tails. We will review these sources and show how distributions with different skew and kurtosis values combine.

Level crossing methodology applied to line-edge roughness characterization

Stochastic-induced roughness of lithographic features continues to be of great concern due to its impact on semiconductor devices. In particular, rare events (large deviations in edge positions due to roughness) can cause catastrophic failure of a chip, but are hard to predict. Here, a new methodology, the level crossing method, is used to characterize the statistical behavior of edge roughness with the goal of predicting extreme events. Using experimental results from EUV lithography, the distribution of edge deviations was found to have tails significantly heavier than a normal distribution. While further work is required, these heavy tails could prove problematic when EUV is used in high volume manufacturing.

Chasing ghosts: How an SRAM detected the subtle impact of stray light

The ever-shrinking world of semiconductors has always challenged the interplay of tool capability, process integration, and characterization. The fine line between structural or electrical success and failure has steadily been redefined from microns to nanometers with leading edge technology using terms with the likes of angstroms and layers of atoms. Failure modes at these nodes become increasing difficult at times to even grasp, let alone “visualize” with electrical and physical analytical techniques. The complexity of these state-of-the-art problem sets demand adaptive and robust problem solving methodologies tailored to uncover and drive root cause understanding. Assembling and organizing diverse teams covering a broad range of expertise becomes paramount. In this case study, we were able to make use of a unique low voltage static random access memory fail mode and spatial fingerprint to chase down a 1 nanometer change in transistor gate line widths; the sleuthing effort concluded with the unlikely combination of mask chrome frame and stray light from lithography as the ultimate root cause.

Vote-taking for EUV lithography: a radical approach to mitigate mask defects

Vote-taking lithography sums up N mask images, each at 1/N dose, to mitigate the mask defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N-1 masks. This paper will explore vote-taking for EUV lithography with both simulation and experimental results. PROLITH simulations will show the size of defects that can be healed for different N, the number of masks. SEM images of NXE 3300 exposures will be shown that are similar to those predicted from simulation. The implementation of vote-taking lithography for High Volume Manufacturing has huge practical and economic barriers. Some expose tool capabilities that could enable vote-taking lithography will be discussed. Besides defect mitigation, we briefly speculate on other possible imaging benefits opened up by voting with several exposure passes.

Intrafield overlay correction for illumination-based distortion

Abstract. The use of different illumination source shapes and multipatterning processes used to generate sub–40-nm images can create image placement errors level to level, resulting in significant intrafield overlay errors. These errors arise because of the impact of the different pupil shapes on lens aberrations resolving into image placement errors as well as because different tools will react differently to the same pupil shapes. We compare the impact of two extreme illumination sources on intrafield image placement and its effect on overall pattern overlay. We also discuss a method to empirically isolate and measure the amount of intrafield overlay distortion relative to a reference illumination source and then use the results to correct the resultant image placement errors.