Anne Vandooren

Fully-depleted SOI devices with TaSiN gate, HfO 2 gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/. The intrinsic low-leakage nature of the FDSOI device and its immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.

Gate-all-around OTA's for rad-hard and high-temperature analog applications

Performance of operational transconductance amplifiers (OTAs) fabricated in the gate-all-around SOI technology is described at elevated temperature and after total dose irradiation. Design guidelines using two analog parameters (early voltage and transconductance to drain current ratio) are proposed for correct operation in these two different harsh environments. The design methodology using the two analog parameters of interest is proposed and applied to the specific case of the GAA technology. The temperature and dose dependence of the two above design parameters are then presented. Two different OTA architectures are considered: a single-stage amplifier and a folded cascode amplifier. Experimental results obtained separately for each environment are discussed. High-temperature measurements were performed up to 300/spl deg/C, while total dose measurements were obtained for doses up to 15 Mrad(Si) total dose of gamma rays from a /sup 60/Co source.

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.

SOI current and voltage reference sources for applications up to 300/spl deg/C

This work presents the potential of fully-depleted SOI technology to implement current and voltage reference sources for very wide temperature range applications. Design of these reference sources is realized using device measurements. Implementation results show temperature coefficient better than 100 ppm from room temperature to 300/spl deg/C.

Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric

In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.

Hall effect measurements in double-gate SOI MOSFETs

The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on I-D/(g(m))(0.5) provides acceptable values for the drift mobility. The experiment reveals high carrier mobility dominated at room temperature by a phonons scattering mechanism and at low temperature by mixed scattering processes, with a predominance of the surface roughness scattering mechanism. No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI films

Carrier lifetime extraction in fully depleted dual-gate SOI devices

A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume.

Gate-All-Around Technology for Harsh Environment Applications

Gate-Ail-Around (GAA) transistors are thin, fully depleted SOI MOSFETs with a double gate structure. When used at high temperature GAA devices present low leakage current, minimal threshold voltage shift and, in general, better characteristics than bulk or even SOI MOSFETs. The radiation hardness of GAA devices is reported as well, and the dose evolution of parameters such as threshold voltage, subthreshold slope and output conductance is analyzed.

Hall mobility measurement in double-gate SOI MOSFETs

Double-gate SOI MOSFETs such as gate-all-around (GAA) (Colinge, 1997) or delta (Hisamoto et al., 1991) structures are considered as strong candidate structures for ultimate ultra-short MOSFETs. These devices benefit from remarkable advantages such as increased drain current, ideal subthreshold swing, reduced short-channel effect and low leakage currents. GAA transistors introduce the concept of volume inversion (Balestra et al., 1987) in which the minority carriers are no longer confined at the interfaces but spread out across the silicon film. The main benefit is the gain in transconductance due to electron transport with volume-like mobility. So far, no direct measurement of mobility in double-gate devices has been reported. In this paper, the electron mobility is extracted from Hall effect measurements, on special double-gate structures, at 300 K and 77 K. This method is also compared to conventional techniques for mobility extraction based on transistor characteristics.