Leo Mathew

Physical insights regarding design and performance of independent-gate FinFETs

Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure.

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

Radio Frequency Transistors and Circuits Based on CVD MoS2

We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

High-Performance Flexible Thin-Film Transistors Exfoliated from Bulk Wafer

Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal-oxide-semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).

A novel low cost 25μm thin exfoliated monocrystalline Si solar cell technology

To achieve grid parity, photovoltaic (PV) technologies must reduce the production cost of PV modules to well below

Top-gated chemical vapor deposited MoS2 field-effect transistors on Si3N4 substrates

1/Wp. In crystalline Si (c-Si) solar cells the cost of raw Si wafers is over 40% of the module cost. There is an industry wide push to reduce the active Si content of the cell through a combination of thinner wafers and increased cell efficiency. However, cell manufacturers are struggling to reduce the wafer thickness below 150μm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. In this paper, we demonstrate for the first time, a novel exfoliation technology capable of producing large area (6-in diameter) 25μm thin flexible mono c-Si foils that will dramatically change the cost structure and form factor of high efficiency-Si solar cells without the yield losses and handling issues that are a major problem for traditional thin Si wafers. An un-optimized single side heterojunction cell has been formed with a 25μm exfoliated c-Si foil, which shows an efficiency of 12.5%. The cell characteristics of a 25μm thin c-Si cell with intrinsic a-Si passivation will be presented in the paper. Simulations show that with optimized texturing of the foil and passivation, higher efficiencies (20%) can be attained. Depending on the starting wafer or ingot thickness a final cell cost of between

Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors

0.46/Wp to

Fully-depleted SOI devices with TaSiN gate, HfO 2 gate dielectric, and elevated source/drain extensions

0.50/Wp can be achieved compared to

The ITFET: A Novel FinFET-Based Hybrid Device

1.1/Wp for todays commercial thick crystalline Si cells.