Anthony G. Domenicucci

An investigation of electrical current induced phase transformations in the NiPtSi/polysilicon system

We studied phase transformations and microstructural changes of NiPtSi/polysilicon fuses programmed with three different current densities (under, optimal, and over programming). Electromigration of NiPt toward the anode occurred in all three cases studied. Achieving high resistance after the fuse programming strongly depends on the kinetics of the electromigration and dopant diffusion processes which operate during the fuse blow. A thick silicide region was formed after electrically programmable fuse programming by the reaction of the electromigrated NiPt with the polysilicon layer underneath. The low tails of the underprogrammed fuses seemed to result from the incomplete electromigration and the incomplete dopant depletion due to the insufficient programming current density, while the depletion of the implanted dopants due to the sufficiently elevated temperature seemed to make the postresistance of the optimally programmed fuse higher. In the overprogrammed fuse, the newly formed silicide seemed to hav...

Observation of stacking faults in strained Si layers

Defects in strained Si layers grown on relaxed SiGe layers were studied using chemical etching and transmission electron microscopy. Defect densities were measured in strained Si layers formed on SiGe buffer layers grown on bulk Si, as well as silicon–germanium-on-insulator substrates. It is found that, in addition to threading dislocations and dislocation pile ups, stacking faults are present in nearly all of the materials studied. The stacking faults are shown to originate in the relaxed SiGe alloy suggesting that they form during the relaxation of the SiGe layer.

Effect of copper on the microstructure and electromigration lifetime of Ti–AlCu–Ti fine lines in the presence of tungsten diffusion barriers

A systematic study was performed of the microstructural and electromigration characteristics of Ti–Al(Cu)–Ti laminate structures fabricated from two metal wiring levels 1 μm in width. The total Cu content in the Al(Cu) core layers was varied from 0.5 to 2.0 wt %. A high degree of 〈111〉 texture was found for all Cu concentrations except for the 0.5 wt % film. Grain size statistics were found to be independent of the Cu concentration. The Al grains were supersaturated with Cu which led to shifts in resistance during low temperature baking and electromigration testing. The electromigration lifetime of stripes connected to large reservoirs of Cu and Al was found to be linearly dependent on the total Cu content, whereas there was a ‘‘roll off’’ in the lifetime of two‐level W stud structures as the Cu content was increased. The activation energy for electromigration induced failure was found to be 0.78–0.93 eV. Resistance shifts during electromigration and temperature only stressing and the microstructural char...

Impact of in situ carbon doping on implant damage and strain relaxation of epitaxial silicon germanium layer on silicon

Implant damage and strain relaxation in thin epitaxial silicon germanium (SiGe) layers on silicon (Si) (001) and their dependence on in situ carbon (C) doping in epitaxial SiGe are studied. For a 65nm SiGe layer with ∼25% germanium (Ge), conventional implants used for p-metal-oxide semiconductor source/drain, halo, and extension led to significant implant damage and strain relaxation. Two defect bands were observed, one close to the surface and the other at SiGe∕Si interface. In situ C doping (1019–1020∕cm3) was found to eliminate the implant damage close to SiGe∕Si interface area and prevent significant strain relaxation.

Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing

Addition of Pt to Ni silicide produces a robust [NixPt(1-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.

Diffusion and Defect Structure in Nitrogen Implanted Silicon

Nitrogen diffusion and defect structure were investigated after medium to high dose nitrogen implantation and anneal. 11 keV N 2 + was implanted into silicon at doses ranging from 2×10 14 to 2×10 15 cm −2 . The samples were annealed with an RTA system from 750°C to 900°C in a nitrogen atmosphere or at 1000°C in an oxidizing ambient. Nitrogen profiles were obtained by SIMS, and cross-section TEM was done on selected samples. TOF-SIMS was carried out in the oxidized samples. For lower doses, most of the nitrogen diffuses out of silicon into the silicon/oxide interface as expected. For the highest dose, a significant portion of the nitrogen still remains in silicon even after the highest thermal budget. This is attributed to the finite capacity of the silicon/oxide interface to trap nitrogen. When the interface gets saturated by nitrogen atoms, nitrogen in silicon can not escape into the interface. Implant doses above 7×10 14 create continuous amorphous layers from the surface. For the 2×10 15 case, there is residual amorphous silicon at the surface even after a 750°C 2 min anneal. After the 900°C 2 min anneal, the silicon fully recrystallizes leaving behind stacking faults at the surface and residual end of range damage.

Characterization of Electrically Pulsed Chromium Disilicide Fusible Links

Fusible links, fabricated from silicon rich chromium disilicide thin films, were subjected to voltage pulses in the 3–6 volt range. An optimum voltage existed at which the fuses blew. Transmission electron microscopy (TEM) was used to study the microstructural characteristics of the fuses both before and after the application of the voltage pulses. The TEM characterization, coupled with electrical and physical measurements, revealed that the mechanism underlying the fuse blow was hole current induced Si electromigration. Below the optimum voltage, the amount of Si transported was insufficient to cause fuse rupture. Above the optimum voltage, the current- voltage characteristics of the fuses became nonlinear and a unique sequence of material phases was formed. The composition of the phases suggests that both thermomigration and electromigration processes were operating at voltages above the optimum voltage.

Dual-Lens Electron Holography for Junction Profiling and Strain Mapping of Semiconductor Devices

Electron microscopes have been used extensively to look at structure at the nanometer scale. Most of the information obtained from electron microscopes is amplitude information. Yet, the phase information of electron microscopy, which can be obtained from off-axis electron holography, provides unique information on electronic structure and structural changes in a wide variety of materials.For the semiconductor industry, junction profiling and strain mapping in Si at high spatial resolution provide information that is critical for further scaling of semiconductor devices. Because of the complex process conditions involved to control the junction position relative to the gate position, determination of junction position at high spatial resolution can help to reduce the cost and cycle time of development. Bright-field holography can measure the phase change of electrons traversing the materials, which is directly related to the mean inner potential of Si, indicating the junction position at the nanometer scale. Furthermore, in recent years stressors have been incorporated into devices to change the semiconductor lattice constant in the channel region and thereby enhance hole and electron mobility. Like the junction definition, the extra processing steps involved to add strain in a device have increased development and manufacturing costs. One way to minimize development cycle time is to monitor, at a nanometer scale, changes in channel deformation resulting from process changes. In 2008, Hytch et al. reported that dark-field holography can provide a promising path to nanometer scale strain mapping [1]. Cooper et al. reported using dark-field holography to measure strain related to different process conditions [2, 3].The requirements of electron holography to inspect the current generation of semiconductor devices are: (1) a fringe width (fringe overlap) in the range of about 100 to 800 nm for an adequate field of view (FOV), (2) fringe spacing between 0.5 and 10 nm for meaningful spatial resolution, (3) visibility of the fringe contrast (10–30%) for useful signal-to-noise ratio, and (4) adjust-ability of both the FOV and the fringe spacing relative to the sample. In previous papers and patent disclosures, we reported that we had developed a dual-lens electron holography method on a JEOL instrument to meet the above requirements, and later we implemented the same method on FEI instruments to provide a similar operational range for electron holography [4–6]. This dual-lens operation allows electron holography to be performed from low to high magnification and provides the FOV and fringe spacing necessary for two-dimensional (2D) junction profiling and strain measurements for devices with various sizes.In this article, we describe the electron optics for this method. We also describe several examples of junction profiling and strain mapping to show how to use dual-lens electron holography to resolve semiconductor device issues at high spatial resolution.

Use of moire fringe patterns to map relaxation in SiGe on insulator structures fabricated on SIMOX substrates

Strain Engineering has become extremely important in the semiconductor industry as a means of achieving device performance enhancement as device scaling runs out of steam. It is important to detect strain as a function of position in device sized areas in order to assess the viability of different process schemes. In the present work, Moire fringe patterns were used to measure and map the relaxation effects in SiGe and Si/SiGe structures fabricated on SIMOX substrates. Initially, measurements of the strain state using the Moire technique were correlated with those obtained by x-ray diffraction for blanket SiGe on insulator films over the range 0.2–0.8%. Using this correlation as a basis, several interesting relaxation characteristics were found on patterned structures. Evidence of a rhombohedral relaxation was seen for rectangular SiGe mesas fabricated by patterning and then homogenizing SiGe/Si bilayers on SIMOX substrates. The magnitude of the relaxation was found to depend of the size of the structure and the distance to the nearest edge. Elastic relaxation of Si lines was also seen. Lastly, evidence of non uniform relaxation was seen in the SiGe template in wide channel areas of silicide-contacted device structures.

A Two-Step Spacer Etch for High-Aspect-Ratio Gate Stack Process

A highly selective nitride etch was developed for gate stack spacer process in advanced memory programs. Based on methyl fluoride chemistry with better than 8:1 selectivity of nitride:oxide, this process exhibits minimal erosion to the underlying RTO thermal oxide for consistent diffusion ion-implant control. As the groundrule changed to 0.175um and below, a two-step etch scheme was employed to maintain the profile control in high-aspect-ratio structures. The stability and repeatability of the process is demonstrated in the SPC chart of the post etch FTA site measurement.