Stephen W. Bedell

Germanium channel MOSFETs: opportunities and challenges

This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-channel MOSFETs are discussed on the basis of our recent results. CMOS-compatible integration approaches of Ge channel devices are presented.

CMOS-integrated high-speed MSM germanium waveguide photodetector.

A compact waveguide-integrated Germanium-on-insulator (GOI) photodetector with 10 +/- 2fF capacitance and operating at 40Gbps is demonstrated. Monolithic integration of thin single-crystalline Ge into front-end CMOS stack was achieved by rapid melt growth during source-drain implant activation anneal.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene

There are numerous studies on the growth of planar films on sp(2)-bonded two-dimensional (2D) layered materials. However, it has been challenging to grow single-crystalline films on 2D materials due to the extremely low surface energy. Recently, buffer-assisted growth of crystalline films on 2D layered materials has been introduced, but the crystalline quality is not comparable with the films grown on sp(3)-bonded three-dimensional materials. Here we demonstrate direct van der Waals epitaxy of high-quality single-crystalline GaN films on epitaxial graphene with low defectivity and surface roughness comparable with that grown on conventional SiC or sapphire substrates. The GaN film is released and transferred onto arbitrary substrates. The post-released graphene/SiC substrate is reused for multiple growth and transfer cycles of GaN films. We demonstrate fully functional blue light-emitting diodes (LEDs) by growing LED stacks on reused graphene/SiC substrates followed by transfer onto plastic tapes.

Kerf-Less Removal of Si, Ge, and III–V Layers by Controlled Spalling to Enable Low-Cost PV Technologies

Kerf-less removal of surface layers of photovoltaic materials including silicon, germanium, and III-Vs is demonstrated by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material, and the controlled removal of a continuous surface layer could be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer. Because the entire process is at room temperature, this technique can be applied to kerf-free ingot dicing, removal of preformed p-n junctions or epitaxial layers, or even completed devices. We successfully demonstrate kerf-free ingot dicing, as well as the removal of III-V single-junction epitaxial layers from a Ge substrate. Solar cells formed on the spalled and transferred single-junction layers showed similar characteristics to nonspalled (bulk) cells, indicating that the quality of the epitaxial layers is not compromised as a result of spalling.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Layer-Resolved Graphene Transfer via Engineered Strain Layers

Monolayer Graphene via Two Transfers Oriented monolayers of graphene containing some bilayer regions can be formed on silicon carbide crystal surfaces, but, to be cost effective, the graphene needs to be exfoliated and transferred to other substrates so that the silicon carbide crystal can be reused. Kim et al. (p. 833, published online 31 October) used a nickel film grown to a thickness designed to impart a particular surface stress as a “handle” to exfoliate the graphene layer for transfer to a silica substrate. An additional gold layer was then used to remove the excess monolayer from the bilayer regions to create a monolayer suitable for electronics applications. A two-step exfoliation process allows multiple transfers of oriented monolayer graphene from a silicon carbide surface. The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

High-efficiency thin-film InGaP/InGaAs/Ge tandem solar cells enabled by controlled spalling technology

In this letter, we demonstrate the effectiveness of the controlled spalling technology for producing high-efficiency (28.7%) thin-film InGaP/(In)GaAs/Ge tandem solar cells. The controlled spalling technique was employed to separate the as-grown solar cell structure from the host Ge wafer followed by its transfer to an arbitrary Si support substrate. The structural and electrical properties of the thin-film tandem cells were examined and compared against those on the original bulk Ge substrate. The comparison of the electrical data suggests the equivalency in cell parameters for both the thin-film (spalled) and bulk (non-spalled) cells, confirming that the controlled spalling technology does maintain the integrity of all layers in such an elaborate solar cell structure.

Improved germanium n+/p junction diodes formed by coimplantation of antimony and phosphorus

Obtaining heavily-doped n-type germanium (Ge) is difficult since n-type dopant activation in Ge is limited to less than 5×1019 cm−3 which is far below the solid solubility limit of phosphorus (P) in Ge. Such poor activation has limited the rectifying properties of n+/p Ge diodes. This work is aimed at understanding the challenge of forming highly rectifying n+/p diode as well as enhancing rectification of n+/p diode by using antimony (Sb) and P coimplantation process. Enhanced n+ doping of greater than 1020 cm−3 in Ge obtained by Sb/P codoping results in enhanced rectification in Ge n+/p junction diode.Obtaining heavily-doped n-type germanium (Ge) is difficult since n-type dopant activation in Ge is limited to less than 5×1019 cm−3 which is far below the solid solubility limit of phosphorus (P) in Ge. Such poor activation has limited the rectifying properties of n+/p Ge diodes. This work is aimed at understanding the challenge of forming highly rectifying n+/p diode as well as enhancing rectification of n+/p diode by using antimony (Sb) and P coimplantation process. Enhanced n+ doping of greater than 1020 cm−3 in Ge obtained by Sb/P codoping results in enhanced rectification in Ge n+/p junction diode.

Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

The hole transport characteristics in partially strained (0.5%) Ge p-channel MOSFETs formed on silicon-germanium-on-insulator (SGOI) substrates were investigated for gate lengths down to 65 nm. We demonstrate that high hole mobility is maintained down to the shortest channel lengths. The channel conductance from these devices is measured and compared to state-of-the-art high-performance Si channel P-MOSFETs.