David Howard Allen

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a silicon-on-insulator (SOI) version of the same technology. Some architectural changes improve CPI, including doubling the L1 instruction and data caches to 128 kB and adding a 256 kB L2 directory. The total transistor count increased from 12 M to 34 M.

A VLSI design methodology for SOI technology

An effective development strategy recognizes the interdependency of product cost, performance, technology, tools, schedule, skills, and other controllable but limited quantities. An efficient design methodology enables tradeoffs between these quantities such that the resulting design point can be implemented in a hardware that is competitive and reaches the marketplace when it is most profitable. SOI technology can provide a competitive edge over a bulk design if the development strategy and design methodology is properly positioned to take full advantage of what SOI offers.