Anthony Sanders

A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces

An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply

Adaptive decision-feedback equalization for band-limited high-speed serial links

A high-speed I/O cell comprising a mixed-signal 8-tap decision-feedback equalizer (DFE) with direct cancellation of the first post-cursor intersymbol interference (ISI) has been implemented in 0.13-/spl mu/m CMOS technology. Based on a joint optimization of algorithms and architecture, a low-complexity architecture has been chosen with respect to a compromise between ISI reduction and implementation complexity. The I/O cell dissipates only 86 mW at the target rate of 6.4 Gbps. It is the core of a high-speed I/O link with adaptive receiver equalization. Due to the residual ISI, the adaptation algorithm has to be modified. The concept has been analyzed by system simulations and verified by measurements of the implemented I/O link.

Speeding up CMOS cameras and optical receivers by improved column multiplexer

A new method to compensate for the column multiplexer (MUS) in photo detector arrays is described and analyzed. It is based on a transimpedance amplifier with improved feedback structure. The focus is on arrays where the photo current is directly used as signal. If this current is transferred to the global transimpedance amplifier by a multiplexer, the resistance of te MUX transistor causes a significant speed degradation. Measurements of a test chip in 0.19micrometers CMOS are presented. It turns out that using the proposed circuit it is possible to almost fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty.