Richard Johannes Luyken

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

Abstract Drift-diffusion simulations have been carried out to investigate the design space for n-channel fully depleted (FD) SOI transistors with undoped channels and midgap gates in the 25–50 nm gate length regime. Gate length, Si-body thickness, source drain doping concentration profile, and spacer width have been varied. Provided that the gate length is larger than 3–4 times the Si-body thickness, we find that the high performance targets of the International Technology Roadmap for Semiconductors can be fulfilled for many different parameter combinations. This means that FD SOI is a suitable technology for devices with feature sizes on this length scale.

Full 3D Process and Device Simulation for FinFET optimization

Based on a state-of-the-art 3D process and device simulation framework, we present an extensive analysis of the impact of FinFET process parameters on the device characteristics. The results compare well with the available experimental data.