Daniel Chillet

Floating-to-fixed-point conversion for digital signal processors

Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.

DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constr

In addition to the high performance requirements inherent to multimedia processings or to W-CDMA, future generation mobile telecommunications brings new constraints to the semiconductor design world. In fact, to support these processings, a system will have to be very flexible, in order to support the various algorithms allowed by the norm and the addition of new services, while keeping an energy consumption level compatible with the portability notion of this system. In order to associate high performances and low energy consumption in a flexible system, we developed a dynamically reconfigurable architecture called DART. The aim of this paper is to present this architecture and to estimate its level of performance and its adequacy with future generation mobile telecommunication systems.

Automatic floating-point to fixed-point conversion for DSP code generation

The development of methodologies for the automatic implementation of floating-point algorithms in fixed-point architectures is required for the minimization of cost, power consumption and time to market of digital signal processing applications. In this paper, a new methodology of implementation in Digital Signal Processors (DSP) under accuracy constraint is presented. In comparison with the existing methodologies, the DSP architecture is completely taken into account for optimizing the execution time under accuracy constraint. The justification and the different stages of our methodology are presented.

Memory module selection for high level synthesis

High level synthesis studies have produced many tools which enable us to design the processing unit of applications. The emergence of new communication services has lead to significant growth in the amount of data to be processed in VLSI chips. It involves to synthesis of memory architecture which enables us to satisfy all the application constraints. To obtain this organization, the first step is to select memory from a component library. This paper suggests a formulation of this problem through a minimization of function under constraints. Our approach takes place after the processing unit synthesis and our methodology can be applied to FPGA chips.

OveRSoC: a framework for the exploration of RTOS for RSoC platforms

This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded Real Time Operating Systems (RTOSs) for Reconfigurable System-on-Chip-based platforms.Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution of OS services on this kind of platform. The experimental results show that our components accurately model the dynamic and deterministic behavior of both application and RTOS.

An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC

Currently, designing low-power complex embedded systems is a main challenge for corporations in a large number of electronic domains. There are multiple motivations which lead designers to consider low-power design such as increasing lifetime, improving battery longevity, limited battery capacity, and temperature constraints. Unfortunately, there is a lack of efficient methodology and accurate tool to obtain power/energy estimation of a complete system at different abstraction levels. This paper presents a global framework for power/energy estimation and optimization of heterogeneous multiprocessor system-on-chip (MPSoC). Within this framework, a power modeling methodology is defined, and an open platform is developed. Our methodology takes into account all the embedded system relevant aspects; the software, the hardware, and the operating system. The platform stands for Open Power and Energy Optimization PLatform and Estimator (Open-PEOPLE). It includes diverse estimation tools with respect to their abstraction levels in order to cover the overall design flow. Starting from functional estimation and down to real boards measurements, our platform helps designers to develop new power models, to explore new architectures, and to apply optimization techniques in order to reduce energy and power consumption of the system. The usefulness and the effectiveness of the proposed power estimation framework is demonstrated through a typical embedded system conceived around the Xilinx Virtex II Pro FPGA platform.

Flexible interconnection network for dynamically and partially reconfigurable architectures

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

Power consumption model for partial and dynamic reconfiguration

In the context of embedded systems development, two important challenges are the efficient use of silicon area and the energy consumption minimization. Hardware accelerated tasks allow to reduce energy consumption of several orders of magnitude, compared to software execution, but these tasks require silicon area and consume power even when they are unused (idle power). Dynamic and Partial Reconfiguration (DPR) brings, to System-on-Chip architectures, an interesting answer by allowing to share a piece of silicon surface between different dedicated accelerators and thus brings the opportunity to reduce power consumption. Nevertheless, many parameters like reconfiguration overhead, accelerator area and performance tradeoff, idle power consumption, etc. make power consumption gain difficult to evaluate. In order to take good implementation choices, it is important to have a precise power and energy consumption estimation of the partial reconfiguration process. In this context, this paper presents a detailed investigation of power consumption of a DPR process using Xilinx ICAP reconfiguration controller. From these results we propose three power models with different complexity/accuracy tradeoffs which helps to analyze the benefits of using accelerated and dynamically reconfigurable tasks in comparison with classical static configuration or full software execution.

UPaRC—Ultra-fast power-aware reconfiguration controller

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers-up to 45 times more efficient.

Multi-algorithm ASIP synthesis and power estimation for DSP applications

Power consumption is an increasingly important parameter in the design of mixed hardware/software systems. This work applies the high-level synthesis technique to multi-algorithms and explores its use as a means of analyzing power consumption from the high level of design. We apply a multi-algorithm synthesis technique to designing an application specific instruction set processor (ASIP) from a customized ASIC. This technique synthesizes selected time constrained algorithms to define a set of DSP applications, designs the corresponding ASIP core, and extracts the specific instruction set. Although not as effective as a DSP core solution, this technique provides much of the circuit flexibility while maintaining an available trade-off between performance and power dissipation. This technique contains three power estimators to assist algorithm integration with the view to optimizing the embedded system: the first acts during the application of usual high-level synthesis steps. The second one is triggered after the complete synthesis of the target algorithm, and the third estimator is based on the instruction set of the designed ASIP core. This technique has been implemented in our framework called BSS (Breizh Synthesis System).