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Dive into the research topics where Egidio Ragonese is active.

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Featured researches published by Egidio Ragonese.


Iet Circuits Devices & Systems | 2009

24-GHz ultra-wideband transmitter for vehicular short-range radar applications

Angelo Scuderi; Egidio Ragonese; Giuseppe Palmisano

This paper presents a 24-GHz transmitter for ultra-wideband short-range radar applications fabricated in a 0.13-µm SiGe:C BiCMOS technology. The circuit is composed of a frequency synthesiser, based on 24-GHz voltage-controlled oscillator in an N-integer phase-locked loop (PLL), a RF switch delivering a 0-dBm output power, and a tunable rectangular pulse generator, whose pulse width covers a range between 0.5 and 1.2 ns. The transmitter has been developed for a flip-chip bumping assembly on a module with an UWB antenna. Assuming a 10.5-dBi antenna gain, it is compliant with European Telecommunications Standards Institute (ETSI) transmission mask and is able to cover the main automotive applications addressing both a resolution better than 0.1 m and maximum unambiguous range of 15 m.


international solid-state circuits conference | 2009

A fully integrated 24GHz UWB radar sensor for automotive applications

Egidio Ragonese; Angelo Scuderi; Vittorio Giammello; Ettore Messina; Giuseppe Palmisano

Radar-based advanced safety systems are crucial to reduce road accidents caused by driver inattention. An actual and pervasive adoption of radar technology requires the development of low-cost Silicon-integrated sensors, including microwave, analog, and digital blocks on a single chip, able to replace existing discrete electronics based on compound semiconductors. Indeed, the considerable advantage of Silicon lies in its natural capability for integration that will enable a higher level of complexity in such sensors. Recent Silicon implementations [1, 2] have proved the maturity of both high-speed bipolar and submicron CMOS processes for multi-GHz applications, such as 24GHz automotive short-range radar (SRR). However, the implementation of a complete radar sensor on a single chip is still very challenging and involves a proper radar architecture (i.e., continuous-wave or pulsed radar), efficient detection methodology, a robust radio front-end structure and customized local DSP. In this scenario, UWB sensors based on analog correlation RX represent an attractive solution for a cost-effective automotive SRR [3].


radio frequency integrated circuits symposium | 2010

Transmitter chipset for 24/77-GHz automotive radar sensors

Vittorio Giammello; Egidio Ragonese; Giuseppe Palmisano

This paper presents a SiGe BiCMOS transmitter chipset for 24/77-GHz automotive radar sensors. The chipset adopts a dual-band architecture consisting of a 24-GHz section for ultra-wideband short-range radar operation, which is able to drive the 77-GHz long-range radar transmitter front-end. The proposed solution allows using a single 24-GHz frequency synthesizer to implement both operation modes. The 77-GHz transmitter demonstrates an output power of 12 dBm, a power gain of 20 dB and an output-referred 1-dB compression point of 11 dBm, while drawing 155 mA from a 2.5-V supply voltage.


radio frequency integrated circuits symposium | 2008

An ultra-wideband transmitter based on a new pulse generator

Marco Cavallaro; Egidio Ragonese; Giuseppe Palmisano

The paper describes an ultra-wideband transmitter, which incorporates an innovative carrier-based pseudo-Gaussian pulse generator satisfying FCC rules with no-filter and high spectral efficiency. The design includes a BPSK modulator, a ramp generator and an output buffer. The transmitter is designed for run up to 500 Mpps in the UWB 3-5-GHz band and it is implemented in 0.28-mum CMOS technology with a core chip size of 0.06-mm2. It allows the use in various UWB applications. Pulse generator dissipation is 1.9-mW.


radio frequency integrated circuits symposium | 2005

The transformer characteristic resistance and its application to the performance analysis of silicon integrated transformers

Alessandro Italia; Francesco Carrara; Egidio Ragonese; Tonio Biondi; Antonino Scuderi; Giuseppe Palmisano

In this paper a novel figure of merit for the rating of integrated transformers is presented. The proposed parameter provides a more reliable performance characterization compared to previously reported ones (i.e., insertion loss and maximum available gain), since it is inherently related to the maximization of the available output power in tuned-load RF circuits. The new figure of merit is used to evaluate the effect of different substrate management approaches on the performance of silicon integrated transformers.


international conference on electronics, circuits, and systems | 2002

A very accurate design of monolithic inductors in a 2D EM simulator

Egidio Ragonese; G. Girlando; Giuseppe Palmisano

This work discusses a strategy for the design of monolithic inductors through 2D EM simulations. Two different types of inductors are considered which were fabricated in a high frequency bipolar silicon process. The first type is an inductor on a traditional substrate with a solid n/sup +/-doped buried layer, the second type is an inductor on a substrate with an oxide honeycomb trenched buried layer. The proposed strategy takes into account substrate effects, return path to ground and electromagnetic coupling with surrounding environment. Inductor performance parameters are accurately predicted up to self-resonance frequency.


mediterranean electrotechnical conference | 2004

Experimental comparison of substrate structures for inductors and transformers

Egidio Ragonese; Angelo Scuderi; Tonio Biondi; Giuseppe Palmisano

An experimental comparison of the substrate structures for silicon inductive devices is proposed. On-wafer measurements for both inductors and stacked transformers revealed that better performance is achieved by exploiting a n/sup +/-doped buried layer as a patterned ground shield. The proposed solution increases inductor quality factor and allows a wide operative bandwidth for transformers to be achieved, as well. Moreover, owing to a well-defined RF ground reference, cross-talk phenomena are inherently reduced. Finally, the buried layer patterned ground shield highly simplifies substrate modeling and allows accurate electromagnetic simulations to be easily carried out.


radio frequency integrated circuits symposium | 2006

A 18-GHz silicon bipolar VCO with transformer-based resonator

Angelo Scuderi; Egidio Ragonese; Tonio Biondi; Giuseppe Palmisano

A silicon bipolar voltage-controlled oscillator for 17-GHz ISM band is presented. The VCO is composed of a core oscillating at 9 GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1 GHz from 16.4 to 20.5 GHz and a phase noise as low as -109 dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5 GHz. To design and optimize the resonator, a lumped scalable model for differentially driven inductors and transformers was used. This model is presented and validated up to 20 GHz by comparison with experimental data


european microwave conference | 2005

Analysis and modeling of thick-metal spiral inductors on silicon

Angelo Scuderi; Tonio Biondi; Egidio Ragonese; Giuseppe Palmisano

In this paper, the analysis and modeling of thick-metal spiral inductors are addressed. The actual improvements of metal thickening in terms of quality factor are evaluated and related to skin and proximity effects. The inductance decrease due to metal thickening is also investigated and modeled using a modified current-sheet expression. The proposed formula achieves higher accuracy compared to the original one revealing errors below 5% even for thickness-to-width ratio up to 2.5.


Telecommunication Systems | 2006

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

Egidio Ragonese; Alessandro Italia; Giuseppe Palmisano

An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of –14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.

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